DE3855342T2 - Digitale Phasenregelschleifen-Anordnung - Google Patents

Digitale Phasenregelschleifen-Anordnung

Info

Publication number
DE3855342T2
DE3855342T2 DE3855342T DE3855342T DE3855342T2 DE 3855342 T2 DE3855342 T2 DE 3855342T2 DE 3855342 T DE3855342 T DE 3855342T DE 3855342 T DE3855342 T DE 3855342T DE 3855342 T2 DE3855342 T2 DE 3855342T2
Authority
DE
Germany
Prior art keywords
locked loop
phase locked
digital phase
loop arrangement
arrangement
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE3855342T
Other languages
English (en)
Other versions
DE3855342D1 (de
Inventor
Kengo Sudoh
Ii Hiroshi Ii Hiroshi
Hiroyuki Matsuoka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP62248725A external-priority patent/JPH0191530A/ja
Priority claimed from JP62281502A external-priority patent/JPH07101846B2/ja
Priority claimed from JP62281501A external-priority patent/JPH07101845B2/ja
Priority claimed from JP62306224A external-priority patent/JPH07114362B2/ja
Priority claimed from JP62328949A external-priority patent/JPH0821856B2/ja
Application filed by Sharp Corp filed Critical Sharp Corp
Publication of DE3855342D1 publication Critical patent/DE3855342D1/de
Application granted granted Critical
Publication of DE3855342T2 publication Critical patent/DE3855342T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H03L7/0991—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider
    • H03L7/0992—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider comprising a counter or a frequency divider
DE3855342T 1987-10-01 1988-09-29 Digitale Phasenregelschleifen-Anordnung Expired - Fee Related DE3855342T2 (de)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
JP62248725A JPH0191530A (ja) 1987-10-01 1987-10-01 デジタルｐｌｌ装置
JP62281502A JPH07101846B2 (ja) 1987-11-07 1987-11-07 デジタルフェーズロックループ装置
JP62281501A JPH07101845B2 (ja) 1987-11-07 1987-11-07 デジタルフェーズロックループ装置
JP62306224A JPH07114362B2 (ja) 1987-12-02 1987-12-02 デジタルフェーズロックループ装置
JP62328949A JPH0821856B2 (ja) 1987-12-24 1987-12-24 デジタルｐｌｌ装置

Publications (2)

Publication Number Publication Date
DE3855342D1 DE3855342D1 (de) 1996-07-11
DE3855342T2 true DE3855342T2 (de) 1997-01-23

Family

ID=27530182

Family Applications (1)

Application Number Title Priority Date Filing Date
DE3855342T Expired - Fee Related DE3855342T2 (de) 1987-10-01 1988-09-29 Digitale Phasenregelschleifen-Anordnung

Country Status (3)

Country Link
US (1) US4916403A (de)
EP (1) EP0310088B1 (de)
DE (1) DE3855342T2 (de)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB8924202D0 (en) * 1989-10-27 1989-12-13 Ncr Co Digital phase lock loop decoder
IT1251352B (it) * 1990-06-27 1995-05-08 St Microelectronics Srl Dispositivo automatico ad ampio spettro operativo per il cambio di frequenza nella deflessione orizzontale di monitor a multisincronismo
JP2758258B2 (ja) * 1990-09-17 1998-05-28 株式会社東芝 電源同期位相固定装置
US5793825A (en) * 1996-03-04 1998-08-11 Motorola, Inc. Method and apparatus for extending an operating frequency range of an instantaneous phase-frequency detector
US5828678A (en) * 1996-04-12 1998-10-27 Avid Technologies, Inc. Digital audio resolving apparatus and method
GB9711374D0 (en) * 1997-06-02 1997-07-30 H Vin Mats E Signal processing
JP3267260B2 (ja) 1999-01-18 2002-03-18 日本電気株式会社 位相同期ループ回路及びそれを使用した周波数変調方法
JP3179429B2 (ja) * 1999-01-29 2001-06-25 日本電気アイシーマイコンシステム株式会社 周波数測定用テスト回路及びそれを備えた半導体集積回路
JP2005094077A (ja) * 2003-09-12 2005-04-07 Rohm Co Ltd クロック生成システム
US7889831B2 (en) * 2007-12-12 2011-02-15 Promos Technologies Pte. Ltd. N-bit shift register controller
US9247896B2 (en) * 2012-01-04 2016-02-02 Nellcor Puritan Bennett Ireland Systems and methods for determining respiration information using phase locked loop
CN104378111B (zh) * 2013-08-12 2017-11-14 龙芯中科技术有限公司 计数器和锁相环

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2354103A1 (de) * 1973-10-29 1975-05-07 Siemens Ag Schaltungsanordnung zur regelung der phasenlage eines taktsignals
JPS5941338B2 (ja) * 1976-05-10 1984-10-06 日本電気株式会社 クロツクパルス再生回路
US4151473A (en) * 1977-11-18 1979-04-24 Harris Corporation Phase detector circuit
DE3025356A1 (de) * 1980-07-04 1982-01-21 Deutsche Itt Industries Gmbh, 7800 Freiburg Schaltungsanordnung zur digitalen phasendifferenz-messung, deren verwendung in einer synchronisierschaltung und entsprechende synchronisierschaltung
JPS57173230A (en) * 1981-04-17 1982-10-25 Hitachi Ltd Phase synchronizing circuit
IT1194538B (it) * 1983-12-23 1988-09-22 Italtel Spa Circuito numerico ad aggancio di fase (pdll)
DE3576630D1 (de) * 1984-09-28 1990-04-19 Toshiba Kawasaki Kk Referenzsignalwiedergabegeraet.
US4634998A (en) * 1985-07-17 1987-01-06 Hughes Aircraft Company Fast phase-lock frequency synthesizer with variable sampling efficiency
IT1184024B (it) * 1985-12-17 1987-10-22 Cselt Centro Studi Lab Telecom Perfezionamenti ai circuiti ad aggancio di fase numerici
JP2581074B2 (ja) * 1987-05-20 1997-02-12 ソニー株式会社 デジタルｐｌｌ回路

Also Published As

Publication number Publication date
US4916403A (en) 1990-04-10
DE3855342D1 (de) 1996-07-11
EP0310088A2 (de) 1989-04-05
EP0310088B1 (de) 1996-06-05
EP0310088A3 (en) 1990-09-12

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee