DE3855255T2 - Anordnung von CMOS-Typ - Google Patents

Anordnung von CMOS-Typ

Info

Publication number
DE3855255T2
DE3855255T2 DE3855255T DE3855255T DE3855255T2 DE 3855255 T2 DE3855255 T2 DE 3855255T2 DE 3855255 T DE3855255 T DE 3855255T DE 3855255 T DE3855255 T DE 3855255T DE 3855255 T2 DE3855255 T2 DE 3855255T2
Authority
DE
Germany
Prior art keywords
arrangement
cmos type
cmos
type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE3855255T
Other languages
English (en)
Other versions
DE3855255D1 (de
Inventor
Donald Mcalpine Kenney
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE3855255D1 publication Critical patent/DE3855255D1/de
Publication of DE3855255T2 publication Critical patent/DE3855255T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222Capacitive arrangements or effects of, or between wiring layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528Geometry or layout of the interconnection structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0921Means for preventing a bipolar, e.g. thyristor, action between the different transistor regions, e.g. Latchup prevention
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B10/00Static random access memory [SRAM] devices
    • H10B10/12Static random access memory [SRAM] devices comprising a MOSFET load element
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Geometry (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
  • Element Separation (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
DE3855255T 1987-12-21 1988-12-05 Anordnung von CMOS-Typ Expired - Fee Related DE3855255T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US13595487A 1987-12-21 1987-12-21

Publications (2)

Publication Number Publication Date
DE3855255D1 DE3855255D1 (de) 1996-06-05
DE3855255T2 true DE3855255T2 (de) 1996-11-21

Family

ID=22470550

Family Applications (1)

Application Number Title Priority Date Filing Date
DE3855255T Expired - Fee Related DE3855255T2 (de) 1987-12-21 1988-12-05 Anordnung von CMOS-Typ

Country Status (3)

Country Link
EP (1) EP0321763B1 (de)
JP (1) JP2610968B2 (de)
DE (1) DE3855255T2 (de)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102007063728B4 (de) 2006-03-07 2018-12-13 Infineon Technologies Ag Halbleiterbauelementanordnung mit einem Trench-Transistor
US8501561B2 (en) 2006-03-07 2013-08-06 Infineon Technologies Ag Method for producing a semiconductor component arrangement comprising a trench transistor
US8779506B2 (en) 2006-03-07 2014-07-15 Infineon Technologies Ag Semiconductor component arrangement comprising a trench transistor

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4463491A (en) * 1982-04-23 1984-08-07 Gte Laboratories Incorporated Method of fabricating a monolithic integrated circuit structure
US4498223A (en) * 1982-04-23 1985-02-12 Gte Laboratories Incorporated Method of fabrication of monolithic integrated circuit structure
JPS6146042A (ja) * 1984-08-10 1986-03-06 Nec Corp 半導体装置
US4593459A (en) * 1984-12-28 1986-06-10 Gte Laboratories Incorporated Monolithic integrated circuit structure and method of fabrication
JPH0770685B2 (ja) * 1985-04-25 1995-07-31 日本電信電話株式会社 相補形mis半導体集積回路
JPH0687500B2 (ja) * 1987-03-26 1994-11-02 日本電気株式会社 半導体記憶装置およびその製造方法

Also Published As

Publication number Publication date
DE3855255D1 (de) 1996-06-05
EP0321763A3 (en) 1990-09-19
JPH01173741A (ja) 1989-07-10
EP0321763A2 (de) 1989-06-28
JP2610968B2 (ja) 1997-05-14
EP0321763B1 (de) 1996-05-01

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee