DE3853963D1 - Basiszelle für eine Gatematrixvorrichtung. - Google Patents

Basiszelle für eine Gatematrixvorrichtung.

Info

Publication number
DE3853963D1
DE3853963D1 DE3853963T DE3853963T DE3853963D1 DE 3853963 D1 DE3853963 D1 DE 3853963D1 DE 3853963 T DE3853963 T DE 3853963T DE 3853963 T DE3853963 T DE 3853963T DE 3853963 D1 DE3853963 D1 DE 3853963D1
Authority
DE
Germany
Prior art keywords
matrix device
base cell
gate matrix
gate
cell
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE3853963T
Other languages
English (en)
Other versions
DE3853963T2 (de
Inventor
Takehide Shirato
Teruo Tazunoki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of DE3853963D1 publication Critical patent/DE3853963D1/de
Application granted granted Critical
Publication of DE3853963T2 publication Critical patent/DE3853963T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits
    • H01L27/11803—Masterslice integrated circuits using field effect technology
    • H01L27/11807—CMOS gate arrays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Geometry (AREA)
  • Manufacturing & Machinery (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
DE3853963T 1987-03-13 1988-03-11 Basiszelle für eine Gatematrixvorrichtung. Expired - Fee Related DE3853963T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62059476A JPS63278248A (ja) 1987-03-13 1987-03-13 ゲ−トアレイの基本セル

Publications (2)

Publication Number Publication Date
DE3853963D1 true DE3853963D1 (de) 1995-07-20
DE3853963T2 DE3853963T2 (de) 1996-03-14

Family

ID=13114394

Family Applications (1)

Application Number Title Priority Date Filing Date
DE3853963T Expired - Fee Related DE3853963T2 (de) 1987-03-13 1988-03-11 Basiszelle für eine Gatematrixvorrichtung.

Country Status (5)

Country Link
US (1) US5031018A (de)
EP (1) EP0282082B1 (de)
JP (1) JPS63278248A (de)
KR (1) KR910001424B1 (de)
DE (1) DE3853963T2 (de)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5670816A (en) * 1989-04-07 1997-09-23 Kabushiki Kaisha Toshiba Semiconductor device
JP2714723B2 (ja) * 1991-03-15 1998-02-16 シャープ株式会社 半導体集積回路装置の製造方法
JP3186084B2 (ja) * 1991-05-24 2001-07-11 日本電気株式会社 半導体メモリー装置
EP0690509A1 (de) * 1994-06-30 1996-01-03 Texas Instruments Incorporated Substratanschluss für eine Gate-Array-Basiszelle und Verfahren zu ihrer Herstellung
EP1045446A3 (de) * 1994-09-30 2000-11-15 Yozan Inc. MOS-Inverter mit einer verengten Kanalbreite
IT1289933B1 (it) * 1997-02-20 1998-10-19 Sgs Thomson Microelectronics Dispositivo di memoria con matrice di celle di memoria in triplo well e relativo procedimento di fabbricazione
JP3061004B2 (ja) * 1997-06-18 2000-07-10 日本電気株式会社 半導体装置
JP3006548B2 (ja) * 1997-06-23 2000-02-07 日本電気株式会社 Ｍｏｓ型半導体読み出し専用メモリ装置
US6071778A (en) * 1998-02-20 2000-06-06 Stmicroelectronics S.R.L. Memory device with a memory cell array in triple well, and related manufacturing process
JP4794030B2 (ja) * 2000-07-10 2011-10-12 ルネサスエレクトロニクス株式会社 半導体装置
US7402846B2 (en) * 2005-10-20 2008-07-22 Atmel Corporation Electrostatic discharge (ESD) protection structure and a circuit using the same

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5851539A (ja) * 1981-09-22 1983-03-26 Nec Corp 集積回路装置
JPS5851939A (ja) * 1981-09-24 1983-03-26 Chiyoda Chem Eng & Constr Co Ltd 重質炭化水素油水素化処理用多孔質担体の製造方法
US4430583A (en) * 1981-10-30 1984-02-07 Bell Telephone Laboratories, Incorporated Apparatus for increasing the speed of a circuit having a string of IGFETs
NL8301629A (nl) * 1983-05-09 1984-12-03 Philips Nv Halfgeleiderinrichting.
JPH0828480B2 (ja) * 1983-09-30 1996-03-21 富士通株式会社 半導体集積回路装置
JPS60152055A (ja) * 1984-01-20 1985-08-10 Matsushita Electric Ind Co Ltd 相補型ｍｏｓ半導体装置
EP0166386A3 (de) * 1984-06-29 1987-08-05 Siemens Aktiengesellschaft Integrierte Schaltung in komplementärer Schaltungstechnik

Also Published As

Publication number Publication date
US5031018A (en) 1991-07-09
EP0282082A3 (en) 1990-07-18
EP0282082B1 (de) 1995-06-14
DE3853963T2 (de) 1996-03-14
KR910001424B1 (ko) 1991-03-05
KR880011923A (ko) 1988-10-31
EP0282082A2 (de) 1988-09-14
JPS63278248A (ja) 1988-11-15

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee