DE3853265D1 - Reduzierung der logischen Weglänge unter Verwendung von Boolescher Minimierung. - Google Patents

Reduzierung der logischen Weglänge unter Verwendung von Boolescher Minimierung.

Info

Publication number
DE3853265D1
DE3853265D1 DE3853265T DE3853265T DE3853265D1 DE 3853265 D1 DE3853265 D1 DE 3853265D1 DE 3853265 T DE3853265 T DE 3853265T DE 3853265 T DE3853265 T DE 3853265T DE 3853265 D1 DE3853265 D1 DE 3853265D1
Authority
DE
Germany
Prior art keywords
reduction
path length
logical path
boolean minimization
boolean
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE3853265T
Other languages
English (en)
Other versions
DE3853265T2 (de
Inventor
David James Hathaway
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE3853265D1 publication Critical patent/DE3853265D1/de
Publication of DE3853265T2 publication Critical patent/DE3853265T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/327—Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Logic Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
DE3853265T 1987-12-02 1988-11-10 Reduzierung der logischen Weglänge unter Verwendung von Boolescher Minimierung. Expired - Fee Related DE3853265T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/127,323 US4916627A (en) 1987-12-02 1987-12-02 Logic path length reduction using boolean minimization

Publications (2)

Publication Number Publication Date
DE3853265D1 true DE3853265D1 (de) 1995-04-13
DE3853265T2 DE3853265T2 (de) 1995-09-14

Family

ID=22429502

Family Applications (1)

Application Number Title Priority Date Filing Date
DE3853265T Expired - Fee Related DE3853265T2 (de) 1987-12-02 1988-11-10 Reduzierung der logischen Weglänge unter Verwendung von Boolescher Minimierung.

Country Status (4)

Country Link
US (1) US4916627A (de)
EP (1) EP0318738B1 (de)
CA (1) CA1287174C (de)
DE (1) DE3853265T2 (de)

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US5257201A (en) * 1987-03-20 1993-10-26 International Business Machines Corporation Method to efficiently reduce the number of connections in a circuit
JPH0650514B2 (ja) * 1988-09-30 1994-06-29 日本電気株式会社 論理回路の自動合成方式
US5461574A (en) * 1989-03-09 1995-10-24 Fujitsu Limited Method of expressing a logic circuit
US5095454A (en) * 1989-05-25 1992-03-10 Gateway Design Automation Corporation Method and apparatus for verifying timing during simulation of digital circuits
US5237513A (en) * 1989-11-20 1993-08-17 Massachusetts Institute Of Technology Optimal integrated circuit generation
US5128871A (en) * 1990-03-07 1992-07-07 Advanced Micro Devices, Inc. Apparatus and method for allocation of resoures in programmable logic devices
JPH03260773A (ja) * 1990-03-09 1991-11-20 Fujitsu Ltd Ｌｓｉの組合せ回路自動合成処理方法
US5258919A (en) * 1990-06-28 1993-11-02 National Semiconductor Corporation Structured logic design method using figures of merit and a flowchart methodology
US5274568A (en) * 1990-12-05 1993-12-28 Ncr Corporation Method of estimating logic cell delay time
US5500808A (en) * 1991-01-24 1996-03-19 Synopsys, Inc. Apparatus and method for estimating time delays using unmapped combinational logic networks
US5524082A (en) * 1991-06-28 1996-06-04 International Business Machines Corporation Redundancy removal using quasi-algebraic methods
US5282147A (en) * 1991-08-02 1994-01-25 International Business Machines Corporation Method and apparatus for optimizing a logic network
US5629859A (en) * 1992-10-21 1997-05-13 Texas Instruments Incorporated Method for timing-directed circuit optimizations
US5649163A (en) * 1992-10-29 1997-07-15 Altera Corporation Method of programming an asynchronous load storage device using a representation of a clear/preset storage device
US5751592A (en) * 1993-05-06 1998-05-12 Matsushita Electric Industrial Co., Ltd. Apparatus and method of supporting functional design of logic circuit and apparatus and method of verifying functional design of logic circuit
JPH0793386A (ja) * 1993-09-28 1995-04-07 Fujitsu Ltd Ｌｓｉ実装設計システム
JP3182036B2 (ja) * 1994-02-16 2001-07-03 松下電器産業株式会社 論理合成方法及び論理合成装置
US5729468A (en) * 1994-04-21 1998-03-17 Quicklogic Corporation Reducing propagation delays in a programmable device
JP3210172B2 (ja) * 1994-05-13 2001-09-17 富士通株式会社 ディレイ・レーシング・エラーリスト出力装置
JP2765506B2 (ja) * 1995-01-30 1998-06-18 日本電気株式会社 論理回路遅延情報保持方式
US5535145A (en) * 1995-02-03 1996-07-09 International Business Machines Corporation Delay model abstraction
US6345378B1 (en) * 1995-03-23 2002-02-05 Lsi Logic Corporation Synthesis shell generation and use in ASIC design
US6334205B1 (en) 1999-02-22 2001-12-25 International Business Machines Corporation Wavefront technology mapping
JP3608970B2 (ja) * 1999-03-16 2005-01-12 富士通株式会社 論理回路
US6763506B1 (en) * 2000-07-11 2004-07-13 Altera Corporation Method of optimizing the design of electronic systems having multiple timing constraints
US20030106030A1 (en) * 2001-12-03 2003-06-05 Keller S. Brandon Method and program product for compressing an electronic circuit model
US6779162B2 (en) 2002-01-07 2004-08-17 International Business Machines Corporation Method of analyzing and filtering timing runs using common timing characteristics
US7313552B2 (en) * 2004-03-19 2007-12-25 Sybase, Inc. Boolean network rule engine
US7346862B2 (en) * 2005-08-19 2008-03-18 Synopsys, Inc. Method and apparatus for optimizing a logic network in a digital circuit
US7877711B2 (en) * 2006-03-01 2011-01-25 Nangate A/S Methods of deriving switch networks
US7739324B1 (en) * 2006-03-22 2010-06-15 Cadence Design Systems, Inc. Timing driven synthesis of sum-of-product functional blocks
TWI529551B (zh) * 2009-09-10 2016-04-11 卡登斯系統設計公司 用於實作圖形可編輯參數化單元之系統及方法
US10216875B2 (en) 2017-02-23 2019-02-26 International Business Machines Corporation Leverage cycle stealing within optimization flows

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US944001A (en) * 1907-05-29 1909-12-21 Wallace Oscar Sheafor Chemical-closet.
US940013A (en) * 1908-08-17 1909-11-16 David J Havenstrite Apparatus for harvesting and cutting plate-ice.
US940020A (en) * 1909-04-14 1909-11-16 Thomas G Plant Lip-turning machine.
US940008A (en) * 1909-06-17 1909-11-16 Julius H Gugler Combined primary and secondary battery system.
US943001A (en) * 1909-07-28 1909-12-14 Lester H Camp Plow-point attachment.
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US3093751A (en) * 1959-08-14 1963-06-11 Sperry Rand Corp Logical circuits
US3622762A (en) * 1969-06-11 1971-11-23 Texas Instruments Inc Circuit design by an automated data processing machine
US3705409A (en) * 1970-12-09 1972-12-05 Ibm Tableau network design system
US4263651A (en) * 1979-05-21 1981-04-21 International Business Machines Corporation Method for determining the characteristics of a logic block graph diagram to provide an indication of path delays between the blocks
US4386403A (en) * 1979-12-31 1983-05-31 International Business Machines Corp. System and method for LSI circuit analysis
US4377849A (en) * 1980-12-29 1983-03-22 International Business Machines Corporation Macro assembler process for automated circuit design
US4541067A (en) * 1982-05-10 1985-09-10 American Microsystems, Inc. Combinational logic structure using PASS transistors
US4566064A (en) * 1982-05-10 1986-01-21 American Microsystems, Inc. Combinational logic structure using PASS transistors
DE3376592D1 (en) * 1982-07-13 1988-06-16 Nec Corp Logic simulator operable on level basis and on logic block basis on each level
WO1985002033A1 (en) * 1983-11-03 1985-05-09 Prime Computer, Inc. Digital system simulation method and apparatus
US4591993A (en) * 1983-11-21 1986-05-27 International Business Machines Corporation Methodology for making logic circuits
US4703435A (en) * 1984-07-16 1987-10-27 International Business Machines Corporation Logic Synthesizer
US4698760A (en) * 1985-06-06 1987-10-06 International Business Machines Method of optimizing signal timing delays and power consumption in LSI circuits
US4754408A (en) * 1985-11-21 1988-06-28 International Business Machines Corporation Progressive insertion placement of elements on an integrated circuit
US4816999A (en) * 1987-05-20 1989-03-28 International Business Machines Corporation Method of detecting constants and removing redundant connections in a logic network

Also Published As

Publication number Publication date
CA1287174C (en) 1991-07-30
EP0318738A2 (de) 1989-06-07
EP0318738A3 (de) 1991-03-20
EP0318738B1 (de) 1995-03-08
US4916627A (en) 1990-04-10
DE3853265T2 (de) 1995-09-14

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee