DE3850916T2 - Verfahren zum anisotropen Ätzen von III-V Materialien: Verwendung zur Oberflächenbehandlung für epitaktische Beschichtung. - Google Patents

Verfahren zum anisotropen Ätzen von III-V Materialien: Verwendung zur Oberflächenbehandlung für epitaktische Beschichtung.

Info

Publication number
DE3850916T2
DE3850916T2 DE3850916T DE3850916T DE3850916T2 DE 3850916 T2 DE3850916 T2 DE 3850916T2 DE 3850916 T DE3850916 T DE 3850916T DE 3850916 T DE3850916 T DE 3850916T DE 3850916 T2 DE3850916 T2 DE 3850916T2
Authority
DE
Germany
Prior art keywords
iii
materials
surface treatment
anisotropic etching
epitaxial coating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE3850916T
Other languages
English (en)
Other versions
DE3850916D1 (de
Inventor
Loic Henry
Claude Vaudry
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Orange SA
Original Assignee
France Telecom SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by France Telecom SA filed Critical France Telecom SA
Application granted granted Critical
Publication of DE3850916D1 publication Critical patent/DE3850916D1/de
Publication of DE3850916T2 publication Critical patent/DE3850916T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H01L21/02005—Preparing bulk and homogeneous wafers
    • H01L21/02008—Multistep processes
    • H01L21/0201—Specific process step
    • H01L21/02019—Chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H01L21/30612—Etching of AIIIBV compounds
    • H01L21/30621—Vapour phase etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical & Material Sciences (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Drying Of Semiconductors (AREA)
  • ing And Chemical Polishing (AREA)
DE3850916T 1987-05-21 1988-05-19 Verfahren zum anisotropen Ätzen von III-V Materialien: Verwendung zur Oberflächenbehandlung für epitaktische Beschichtung. Expired - Fee Related DE3850916T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR8707135A FR2615655B1 (fr) 1987-05-21 1987-05-21 Procede de gravure anisotrope d'un materiau iii-v : application au traitement de surface en vue d'une croissance epitaxiale

Publications (2)

Publication Number Publication Date
DE3850916D1 DE3850916D1 (de) 1994-09-08
DE3850916T2 true DE3850916T2 (de) 1995-03-02

Family

ID=9351298

Family Applications (1)

Application Number Title Priority Date Filing Date
DE3850916T Expired - Fee Related DE3850916T2 (de) 1987-05-21 1988-05-19 Verfahren zum anisotropen Ätzen von III-V Materialien: Verwendung zur Oberflächenbehandlung für epitaktische Beschichtung.

Country Status (5)

Country Link
US (1) US5074955A (de)
EP (1) EP0292390B1 (de)
JP (1) JPS6479389A (de)
DE (1) DE3850916T2 (de)
FR (1) FR2615655B1 (de)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5017511A (en) * 1989-07-10 1991-05-21 Texas Instruments Incorporated Method for dry etching vias in integrated circuit layers
US5236547A (en) * 1990-09-25 1993-08-17 Kabushiki Kaisha Toshiba Method of forming a pattern in semiconductor device manufacturing process
US5187110A (en) * 1990-10-05 1993-02-16 Allied-Signal Inc. Field effect transistor-bipolar transistor darlington pair
US5248386A (en) * 1991-02-08 1993-09-28 Aluminum Company Of America Milling solution and method
FR2673330B1 (fr) * 1991-02-26 1997-06-20 France Telecom Procede de realisation d'un laser a semiconducteur a ruban enterre, utilisant une gravure seche pour former ce ruban, et laser obtenu par ce procede.
EP0503473A3 (en) * 1991-03-12 1992-10-28 Texas Instruments Incorporated Method of dry etching ina1as and ingaas lattice matched to inp
US5300452A (en) * 1991-12-18 1994-04-05 U.S. Philips Corporation Method of manufacturing an optoelectronic semiconductor device
US5338394A (en) * 1992-05-01 1994-08-16 Alliedsignal Inc. Method for etching indium based III-V compound semiconductors
US5851725A (en) * 1993-01-26 1998-12-22 The United States Of America As Represented By The Secretary Of Commerce Exposure of lithographic resists by metastable rare gas atoms
US5478437A (en) * 1994-08-01 1995-12-26 Motorola, Inc. Selective processing using a hydrocarbon and hydrogen
GB9616225D0 (en) * 1996-08-01 1996-09-11 Surface Tech Sys Ltd Method of surface treatment of semiconductor substrates
FR2789804B1 (fr) * 1999-02-17 2002-08-23 France Telecom Procede de gravure anisotrope par plasma gazeux d'un materiau polymere dielectrique organique et application a la microelectronique
US9029246B2 (en) * 2013-07-30 2015-05-12 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of forming epitaxial structures
JP2016134519A (ja) * 2015-01-20 2016-07-25 東京エレクトロン株式会社 Ｉｉｉ−ｖ族半導体のエッチング方法及びエッチング装置

Also Published As

Publication number Publication date
EP0292390B1 (de) 1994-08-03
US5074955A (en) 1991-12-24
FR2615655A1 (fr) 1988-11-25
EP0292390A1 (de) 1988-11-23
DE3850916D1 (de) 1994-09-08
FR2615655B1 (fr) 1989-06-30
JPS6479389A (en) 1989-03-24

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee