DE3850447T2 - Asynchrone Übertragungssysteme. - Google Patents

Asynchrone Übertragungssysteme.

Info

Publication number
DE3850447T2
DE3850447T2 DE3850447T DE3850447T DE3850447T2 DE 3850447 T2 DE3850447 T2 DE 3850447T2 DE 3850447 T DE3850447 T DE 3850447T DE 3850447 T DE3850447 T DE 3850447T DE 3850447 T2 DE3850447 T2 DE 3850447T2
Authority
DE
Germany
Prior art keywords
transmission systems
asynchronous transmission
asynchronous
systems
transmission
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE3850447T
Other languages
English (en)
Other versions
DE3850447D1 (de
Inventor
Hugo Rowton C O Dynami Simpson
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
MBDA UK Ltd
Original Assignee
British Aerospace PLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by British Aerospace PLC filed Critical British Aerospace PLC
Application granted granted Critical
Publication of DE3850447D1 publication Critical patent/DE3850447D1/de
Publication of DE3850447T2 publication Critical patent/DE3850447T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/16—Multiplexed systems, i.e. using two or more similar devices which are alternately accessed for enqueue and dequeue operations, e.g. ping-pong buffers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/54—Interprogram communication
    • G06F9/544—Buffers; Shared memory; Pipes

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Memory System (AREA)
DE3850447T 1987-05-21 1988-05-19 Asynchrone Übertragungssysteme. Expired - Lifetime DE3850447T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB878711991A GB8711991D0 (en) 1987-05-21 1987-05-21 Asynchronous communication systems

Publications (2)

Publication Number Publication Date
DE3850447D1 DE3850447D1 (de) 1994-08-04
DE3850447T2 true DE3850447T2 (de) 1994-11-03

Family

ID=10617678

Family Applications (1)

Application Number Title Priority Date Filing Date
DE3850447T Expired - Lifetime DE3850447T2 (de) 1987-05-21 1988-05-19 Asynchrone Übertragungssysteme.

Country Status (5)

Country Link
US (1) US4875224A (de)
EP (1) EP0292287B1 (de)
JP (1) JPH01119841A (de)
DE (1) DE3850447T2 (de)
GB (1) GB8711991D0 (de)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5208913A (en) * 1988-06-22 1993-05-04 Sharp Kabushiki Kaisha Buffer memory for synchronizing data transmission and reception between two devices having mutually different operating speeds and operating methods therefor
GB9008366D0 (en) * 1990-04-12 1990-06-13 British Aerospace Data interaction architecture(dia)for real time embedded multi processor systems
JP2821345B2 (ja) * 1993-09-29 1998-11-05 北海道日本電気ソフトウェア株式会社 非同期ｉ／ｏ制御方式
US5680608A (en) * 1995-02-06 1997-10-21 International Business Machines Corporation Method and system for avoiding blocking in a data processing system having a sort-merge network
WO2000005644A1 (en) * 1998-07-22 2000-02-03 California Institute Of Technology Reshuffled communications processes in pipelined asynchronous circuits
US6286076B1 (en) 1999-01-05 2001-09-04 Sun Microsystems, Inc. High speed memory-based buffer and system and method for use thereof
US7283557B2 (en) * 2002-01-25 2007-10-16 Fulcrum Microsystems, Inc. Asynchronous crossbar with deterministic or arbitrated control
US7698535B2 (en) 2002-09-16 2010-04-13 Fulcrum Microsystems, Inc. Asynchronous multiple-order issue system architecture
US7260753B2 (en) * 2003-07-14 2007-08-21 Fulcrum Microsystems, Inc. Methods and apparatus for providing test access to asynchronous circuits and systems
US7584449B2 (en) * 2004-11-22 2009-09-01 Fulcrum Microsystems, Inc. Logic synthesis of multi-level domino asynchronous pipelines
US7733857B2 (en) * 2004-12-17 2010-06-08 Samsung Electronics Co., Ltd. Apparatus and method for sharing variables and resources in a multiprocessor routing node
US7814280B2 (en) * 2005-01-12 2010-10-12 Fulcrum Microsystems Inc. Shared-memory switch fabric architecture
US20080126956A1 (en) * 2006-08-04 2008-05-29 Kodosky Jeffrey L Asynchronous Wires for Graphical Programming
EP1956484B1 (de) * 2007-02-07 2011-10-19 Robert Bosch Gmbh Verwaltungsmodul, Hersteller- und Verbraucherrechner, Anordnung davon und Verfahren zur Kommunikation zwischen Rechnern über einen gemeinsam verwendeten Speicher
US7916718B2 (en) * 2007-04-19 2011-03-29 Fulcrum Microsystems, Inc. Flow and congestion control in switch architectures for multi-hop, memory efficient fabrics
US8135879B2 (en) * 2009-04-03 2012-03-13 National Instruments Corporation Four-slot asynchronous communication mechanism with increased throughput
US20190138242A1 (en) * 2017-11-08 2019-05-09 Raytheon Company Lock-free asynchronous buffer
EP4123969A1 (de) 2021-07-19 2023-01-25 Ratier-Figeac SAS Umstellungsmechanismus für asynchrone vorrichtungen

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL7201920A (de) * 1972-02-15 1973-08-17 Philips Nv
GB1487706A (en) * 1976-01-16 1977-10-05 Plessey Co Ltd Data storage arrangement for buffering asynchronous input and output data streams
JPS52129341A (en) * 1976-04-23 1977-10-29 Nec Corp Data buffer circuit
FR2440058A1 (fr) * 1978-10-27 1980-05-23 Materiel Telephonique Systeme de memoire tampon pour unite d'echange entre deux unites fonctionnelles et procede de mise en oeuvre
JPS6057090B2 (ja) * 1980-09-19 1985-12-13 株式会社日立製作所 データ記憶装置およびそれを用いた処理装置
JPS57182838A (en) * 1981-05-08 1982-11-10 Victor Co Of Japan Ltd Digital data connecting circuit
JPS6214226A (ja) * 1985-07-12 1987-01-22 Hitachi Ltd 半導体メモリ装置

Also Published As

Publication number Publication date
GB8711991D0 (en) 1987-06-24
EP0292287B1 (de) 1994-06-29
EP0292287A3 (en) 1990-07-18
US4875224A (en) 1989-10-17
EP0292287A2 (de) 1988-11-23
JPH01119841A (ja) 1989-05-11
DE3850447D1 (de) 1994-08-04

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: MATRA BAE DYNAMICS (UK) LTD., STEVENAGE, HERTFORDS

8327 Change in the person/name/address of the patent owner

Owner name: MBDA UK LTD., STEVENAGE, HERTFORDSHIRE, GB