DE3825028A1 - Verfahren und vorrichtung zur ungueltigkeitsoperation bei adressumsetzpuffern in computersystemen - Google Patents

Verfahren und vorrichtung zur ungueltigkeitsoperation bei adressumsetzpuffern in computersystemen

Info

Publication number
DE3825028A1
DE3825028A1 DE3825028A DE3825028A DE3825028A1 DE 3825028 A1 DE3825028 A1 DE 3825028A1 DE 3825028 A DE3825028 A DE 3825028A DE 3825028 A DE3825028 A DE 3825028A DE 3825028 A1 DE3825028 A1 DE 3825028A1
Authority
DE
Germany
Prior art keywords
information
address
virtual
vmid
holding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
DE3825028A
Other languages
German (de)
English (en)
Other versions
DE3825028C2 (https=
Inventor
Mari Ara
Hideo Sawamoto
Ryo Yamagata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Publication of DE3825028A1 publication Critical patent/DE3825028A1/de
Application granted granted Critical
Publication of DE3825028C2 publication Critical patent/DE3825028C2/de
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G06F12/1036—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] for multiple virtual address spaces, e.g. segmentation

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
DE3825028A 1987-07-24 1988-07-22 Verfahren und vorrichtung zur ungueltigkeitsoperation bei adressumsetzpuffern in computersystemen Granted DE3825028A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62183322A JP2510605B2 (ja) 1987-07-24 1987-07-24 仮想計算機システム

Publications (2)

Publication Number Publication Date
DE3825028A1 true DE3825028A1 (de) 1989-02-02
DE3825028C2 DE3825028C2 (https=) 1993-01-07

Family

ID=16133676

Family Applications (1)

Application Number Title Priority Date Filing Date
DE3825028A Granted DE3825028A1 (de) 1987-07-24 1988-07-22 Verfahren und vorrichtung zur ungueltigkeitsoperation bei adressumsetzpuffern in computersystemen

Country Status (3)

Country Link
US (1) US5317710A (https=)
JP (1) JP2510605B2 (https=)
DE (1) DE3825028A1 (https=)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7890731B2 (en) 2003-05-12 2011-02-15 International Business Machines Corporation Clearing selected storage translation buffer entries based on table origin address
US9182984B2 (en) 2012-06-15 2015-11-10 International Business Machines Corporation Local clearing control
US9454490B2 (en) 2003-05-12 2016-09-27 International Business Machines Corporation Invalidating a range of two or more translation table entries and instruction therefore

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07248974A (ja) * 1994-03-10 1995-09-26 Hitachi Ltd 情報処理装置
JPH0981459A (ja) * 1995-09-19 1997-03-28 Hitachi Ltd アドレス変換バッファ装置
DE19717102A1 (de) * 1997-04-23 1998-10-29 Siemens Nixdorf Inf Syst Verfahren zur Übertragung eines Betriebssystems in Datenverarbeitungsanlagen
JP2001051900A (ja) * 1999-08-17 2001-02-23 Hitachi Ltd 仮想計算機方式の情報処理装置及びプロセッサ
EP1391820A3 (en) * 2002-07-31 2007-12-19 Texas Instruments Incorporated Concurrent task execution in a multi-processor, single operating system environment
US7069413B1 (en) 2003-01-29 2006-06-27 Vmware, Inc. Method and system for performing virtual to physical address translations in a virtual machine monitor
US7530067B2 (en) * 2003-05-12 2009-05-05 International Business Machines Corporation Filtering processor requests based on identifiers
JP4718869B2 (ja) * 2005-03-11 2011-07-06 エヌイーシーコンピュータテクノ株式会社 エミュレータ、エミュレータにおけるアドレス計算例外検出方法、プログラム
CN100447702C (zh) * 2005-05-23 2008-12-31 联想(北京)有限公司 一种防止未被授权程序在计算机系统运行的方法及其系统
US7480784B2 (en) * 2005-08-12 2009-01-20 Advanced Micro Devices, Inc. Ensuring deadlock free operation for peer to peer traffic in an input/output memory management unit (IOMMU)
US7793067B2 (en) * 2005-08-12 2010-09-07 Globalfoundries Inc. Translation data prefetch in an IOMMU
US7543131B2 (en) * 2005-08-12 2009-06-02 Advanced Micro Devices, Inc. Controlling an I/O MMU
US7548999B2 (en) * 2006-01-17 2009-06-16 Advanced Micro Devices, Inc. Chained hybrid input/output memory management unit
EP2169557A4 (en) * 2007-06-20 2010-08-04 Fujitsu Ltd PROCESSOR, TLB CONTROL PROCEDURE, TLB CONTROL PROGRAM AND INFORMATION PROCESSOR
US8631212B2 (en) 2011-09-25 2014-01-14 Advanced Micro Devices, Inc. Input/output memory management unit with protection mode for preventing memory access by I/O devices
US9619387B2 (en) * 2014-02-21 2017-04-11 Arm Limited Invalidating stored address translations
US9626221B2 (en) 2015-02-24 2017-04-18 Red Hat Israel, Ltd. Dynamic guest virtual machine identifier allocation

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0657449A (ja) * 1992-08-11 1994-03-01 Sumitomo Metal Ind Ltd 耐食性と溶接性に優れた自動車用高強度めっき鋼板

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4053948A (en) * 1976-06-21 1977-10-11 Ibm Corporation Look aside array invalidation mechanism
US4426682A (en) * 1981-05-22 1984-01-17 Harris Corporation Fast cache flush mechanism
US4456954A (en) * 1981-06-15 1984-06-26 International Business Machines Corporation Virtual machine system with guest architecture emulation using hardware TLB's for plural level address translations
US4714990A (en) * 1982-09-18 1987-12-22 International Computers Limited Data storage apparatus
US4731739A (en) * 1983-08-29 1988-03-15 Amdahl Corporation Eviction control apparatus
US4682281A (en) * 1983-08-30 1987-07-21 Amdahl Corporation Data storage unit employing translation lookaside buffer pointer
JPS6091462A (ja) * 1983-10-26 1985-05-22 Toshiba Corp 演算制御装置
US4779188A (en) * 1983-12-14 1988-10-18 International Business Machines Corporation Selective guest system purge control
JPS60209862A (ja) * 1984-02-29 1985-10-22 Panafacom Ltd アドレス変換制御方式
GB8405491D0 (en) * 1984-03-02 1984-04-04 Hemdal G Computers
JPS61206057A (ja) * 1985-03-11 1986-09-12 Hitachi Ltd アドレス変換装置
JPH0685156B2 (ja) * 1985-05-24 1994-10-26 株式会社日立製作所 アドレス変換装置
JPH0658650B2 (ja) * 1986-03-14 1994-08-03 株式会社日立製作所 仮想計算機システム
US4843541A (en) * 1987-07-29 1989-06-27 International Business Machines Corporation Logical resource partitioning of a data processing system

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0657449A (ja) * 1992-08-11 1994-03-01 Sumitomo Metal Ind Ltd 耐食性と溶接性に優れた自動車用高強度めっき鋼板

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7890731B2 (en) 2003-05-12 2011-02-15 International Business Machines Corporation Clearing selected storage translation buffer entries based on table origin address
US8122224B2 (en) 2003-05-12 2012-02-21 International Business Machines Corporation Clearing selected storage translation buffer entries bases on table origin address
US8452942B2 (en) 2003-05-12 2013-05-28 International Business Machines Corporation Invalidating a range of two or more translation table entries and instruction therefore
US9454490B2 (en) 2003-05-12 2016-09-27 International Business Machines Corporation Invalidating a range of two or more translation table entries and instruction therefore
US9182984B2 (en) 2012-06-15 2015-11-10 International Business Machines Corporation Local clearing control

Also Published As

Publication number Publication date
DE3825028C2 (https=) 1993-01-07
US5317710A (en) 1994-05-31
JP2510605B2 (ja) 1996-06-26
JPS6428758A (en) 1989-01-31

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Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
D2 Grant after examination
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee