DE3785209D1 - Datenverarbeitungssystem mit einer schnellen unterbrechung. - Google Patents
Datenverarbeitungssystem mit einer schnellen unterbrechung.Info
- Publication number
- DE3785209D1 DE3785209D1 DE8787115019T DE3785209T DE3785209D1 DE 3785209 D1 DE3785209 D1 DE 3785209D1 DE 8787115019 T DE8787115019 T DE 8787115019T DE 3785209 T DE3785209 T DE 3785209T DE 3785209 D1 DE3785209 D1 DE 3785209D1
- Authority
- DE
- Germany
- Prior art keywords
- interface
- interrupt
- command
- coupled
- cpu
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
- G06F13/26—Handling requests for interconnection or transfer for access to input/output bus using interrupt with priority control
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
- G06F15/17—Interprocessor communication using an input/output type connection, e.g. channel, I/O port
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Software Systems (AREA)
- Bus Control (AREA)
- Hardware Redundancy (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP87115019A EP0311705B1 (de) | 1987-10-14 | 1987-10-14 | Datenverarbeitungssystem mit einer schnellen Unterbrechung |
Publications (2)
Publication Number | Publication Date |
---|---|
DE3785209D1 true DE3785209D1 (de) | 1993-05-06 |
DE3785209T2 DE3785209T2 (de) | 1993-11-04 |
Family
ID=8197358
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE19873785209 Expired - Lifetime DE3785209T2 (de) | 1987-10-14 | 1987-10-14 | Datenverarbeitungssystem mit einer schnellen unterbrechung. |
Country Status (3)
Country | Link |
---|---|
EP (1) | EP0311705B1 (de) |
DE (1) | DE3785209T2 (de) |
ES (1) | ES2040230T3 (de) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07104842B2 (ja) * | 1989-03-03 | 1995-11-13 | 日本電気株式会社 | 外部記憶装置の割込み制御方式 |
DE3917715A1 (de) * | 1989-05-31 | 1990-12-06 | Teldix Gmbh | Rechnersystem |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3993981A (en) * | 1975-06-30 | 1976-11-23 | Honeywell Information Systems, Inc. | Apparatus for processing data transfer requests in a data processing system |
US4023143A (en) * | 1975-10-28 | 1977-05-10 | Cincinnati Milacron Inc. | Fixed priority interrupt control circuit |
US4080649A (en) * | 1976-12-16 | 1978-03-21 | Honeywell Information Systems Inc. | Balancing the utilization of I/O system processors |
US4200912A (en) * | 1978-07-31 | 1980-04-29 | Motorola, Inc. | Processor interrupt system |
US4807117A (en) * | 1983-07-19 | 1989-02-21 | Nec Corporation | Interruption control apparatus |
-
1987
- 1987-10-14 EP EP87115019A patent/EP0311705B1/de not_active Expired - Lifetime
- 1987-10-14 DE DE19873785209 patent/DE3785209T2/de not_active Expired - Lifetime
- 1987-10-14 ES ES87115019T patent/ES2040230T3/es not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
ES2040230T3 (es) | 1993-10-16 |
DE3785209T2 (de) | 1993-11-04 |
EP0311705B1 (de) | 1993-03-31 |
EP0311705A1 (de) | 1989-04-19 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US4504906A (en) | Multiprocessor system | |
ES481514A1 (es) | Un aparato controlador de entrada-salida para transferir da-tos entre un ordenador central y una o mas unidades de en- trada-salida. | |
JPS55112651A (en) | Virtual computer system | |
DE69325106D1 (de) | Bereitschaftssystem für rechnerbildschirm mit niedrigem energieverbrauch | |
JPS6446135A (en) | Central processor for digital computer | |
DE3688363D1 (de) | Unterbrechungsabwicklung in einem multiprozessorrechnersystem. | |
US4084233A (en) | Microcomputer apparatus | |
DE3785209D1 (de) | Datenverarbeitungssystem mit einer schnellen unterbrechung. | |
NO175120C (no) | Systemlederanordning for databehandlingssystem | |
EP0268342A1 (de) | Koordination des Verarbeitungselemente in einem Multiprozessorrechner | |
KR100350970B1 (ko) | 운영체제타이머에초기값설정방법 | |
GB2303949A (en) | Computer system with peripheral control functions integrated into host CPU | |
JPS62150416A (ja) | 低消費電力状態への移行方式 | |
JPS5556235A (en) | Initializing method of terminal controller on decentralized control system | |
JPS55103656A (en) | Information processing system | |
JPS57161962A (en) | Communicating method between processors | |
JPS5720847A (en) | Computer system | |
EP0278263A3 (de) | Mehrfachbus-Direktspeicherzugriffssteuerungsgerät | |
JPS5750046A (en) | Data transmission system | |
JPS56121168A (en) | Common resource control system of multiple central processing unit system etc | |
JPS54145447A (en) | Input-output control system | |
JPS6423359A (en) | Advance reading switch system | |
JPS6437649A (en) | Input/output control system | |
JPS55154622A (en) | Input and output managing system in multiprocessor system | |
JPS57123454A (en) | Microprogram computer |