ES2040230T3 - Sistema de tratamiento de datos con una interrupcion rapida. - Google Patents
Sistema de tratamiento de datos con una interrupcion rapida.Info
- Publication number
- ES2040230T3 ES2040230T3 ES87115019T ES87115019T ES2040230T3 ES 2040230 T3 ES2040230 T3 ES 2040230T3 ES 87115019 T ES87115019 T ES 87115019T ES 87115019 T ES87115019 T ES 87115019T ES 2040230 T3 ES2040230 T3 ES 2040230T3
- Authority
- ES
- Spain
- Prior art keywords
- interruption
- command
- system bus
- current
- data processing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
- G06F13/26—Handling requests for interconnection or transfer for access to input/output bus using interrupt with priority control
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
- G06F15/17—Interprocessor communication using an input/output type connection, e.g. channel, I/O port
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Software Systems (AREA)
- Bus Control (AREA)
- Hardware Redundancy (AREA)
Abstract
UN SISTEMA MULTIPROCESADOR INCLUYE UN NUMERO DE SUBSISTEMAS TODOS ELLOS ACOPLADOS EN COMUN A UN BUS DE SISTEMA ASINCRONO. UN APARATO SE INCLUYE EN LA LOGICA DEL INTERFACE DEL BUS DEL SISTEMA DE CADA SUBSISTEMA DE PROCESO PARA RECIBIR LOS COMANDOS DESDE EL BUS DEL SISTEMA Y COMPARA EL NIVEL DE PRIORIDAD DE INTERRUPCION DEL NUEVO COMANDO CON EL COMANDO ACTUAL QUE SE ESTA EJECUTANDO. SI EL NUEVO COMANDO TIENE UNA PRIORIDAD DE INTERRUPCION INFERIOR QUE EL COMANDO ACTUAL, ENTONCES EL SUBSISTEMA QUE ENVIA EL COMANDO RECIBIRA UNA RESPUESTA DE NO RECONOCIMIENTO DEL SISTEMA DE PROCESO. EL APARATO ES SENSIBLE A CIERTAS SEÑALES DE CONTROL DEL NUEVO COMANDO PARA PASAR POR ALTO LA LOGICA DE LA COMPARACION DE PRIORIDAD DE INTERRUPCION E INICIAR UNA INTERRUPCION INMEDIATA SIN HACER CASO DEL NIVEL DE PRIORIDAD DE INTERRUPCION DEL COMANDO ACTUAL QUE SE ESTA EJECUTANDO EN EL SISTEMA DE PROCESO. EL SISTEMA DE PROCESO PUEDE TAMBIEN GENERAR UN COMANDO PARA SI MISMO POR MEDIO DEL BUS DEL SISTEMA QUE REQUIERE LAINTERRUPCION DE ALTA VELOCIDAD.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP87115019A EP0311705B1 (en) | 1987-10-14 | 1987-10-14 | Data processing system with a fast interrupt |
Publications (1)
Publication Number | Publication Date |
---|---|
ES2040230T3 true ES2040230T3 (es) | 1993-10-16 |
Family
ID=8197358
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
ES87115019T Expired - Lifetime ES2040230T3 (es) | 1987-10-14 | 1987-10-14 | Sistema de tratamiento de datos con una interrupcion rapida. |
Country Status (3)
Country | Link |
---|---|
EP (1) | EP0311705B1 (es) |
DE (1) | DE3785209T2 (es) |
ES (1) | ES2040230T3 (es) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07104842B2 (ja) * | 1989-03-03 | 1995-11-13 | 日本電気株式会社 | 外部記憶装置の割込み制御方式 |
DE3917715A1 (de) * | 1989-05-31 | 1990-12-06 | Teldix Gmbh | Rechnersystem |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3993981A (en) * | 1975-06-30 | 1976-11-23 | Honeywell Information Systems, Inc. | Apparatus for processing data transfer requests in a data processing system |
US4023143A (en) * | 1975-10-28 | 1977-05-10 | Cincinnati Milacron Inc. | Fixed priority interrupt control circuit |
US4080649A (en) * | 1976-12-16 | 1978-03-21 | Honeywell Information Systems Inc. | Balancing the utilization of I/O system processors |
US4200912A (en) * | 1978-07-31 | 1980-04-29 | Motorola, Inc. | Processor interrupt system |
US4807117A (en) * | 1983-07-19 | 1989-02-21 | Nec Corporation | Interruption control apparatus |
-
1987
- 1987-10-14 ES ES87115019T patent/ES2040230T3/es not_active Expired - Lifetime
- 1987-10-14 EP EP87115019A patent/EP0311705B1/en not_active Expired - Lifetime
- 1987-10-14 DE DE19873785209 patent/DE3785209T2/de not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
EP0311705B1 (en) | 1993-03-31 |
DE3785209D1 (de) | 1993-05-06 |
DE3785209T2 (de) | 1993-11-04 |
EP0311705A1 (en) | 1989-04-19 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
FG2A | Definitive protection |
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