DE3784984D1 - Verfahren zum herstellen von leiterbahnen beim cvd-metall. - Google Patents

Verfahren zum herstellen von leiterbahnen beim cvd-metall.

Info

Publication number
DE3784984D1
DE3784984D1 DE8787401753T DE3784984T DE3784984D1 DE 3784984 D1 DE3784984 D1 DE 3784984D1 DE 8787401753 T DE8787401753 T DE 8787401753T DE 3784984 T DE3784984 T DE 3784984T DE 3784984 D1 DE3784984 D1 DE 3784984D1
Authority
DE
Germany
Prior art keywords
conductive material
layer
recesses
conductor
cvd metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8787401753T
Other languages
English (en)
Other versions
DE3784984T2 (de
Inventor
Jean-Marie Gutierrez
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Digital Equipment Corp
Original Assignee
Digital Equipment Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Digital Equipment Corp filed Critical Digital Equipment Corp
Application granted granted Critical
Publication of DE3784984D1 publication Critical patent/DE3784984D1/de
Publication of DE3784984T2 publication Critical patent/DE3784984T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Chemical Vapour Deposition (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Superconductors And Manufacturing Methods Therefor (AREA)
DE87401753T 1986-07-29 1987-07-28 Verfahren zum Herstellen von Leiterbahnen beim CVD-Metall. Expired - Fee Related DE3784984T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US89197286A 1986-07-29 1986-07-29

Publications (2)

Publication Number Publication Date
DE3784984D1 true DE3784984D1 (de) 1993-04-29
DE3784984T2 DE3784984T2 (de) 1993-10-14

Family

ID=25399146

Family Applications (1)

Application Number Title Priority Date Filing Date
DE87401753T Expired - Fee Related DE3784984T2 (de) 1986-07-29 1987-07-28 Verfahren zum Herstellen von Leiterbahnen beim CVD-Metall.

Country Status (7)

Country Link
EP (1) EP0256917B1 (de)
JP (1) JPS63100745A (de)
KR (1) KR960008522B1 (de)
AT (1) ATE87396T1 (de)
AU (1) AU7620687A (de)
CA (1) CA1269285A (de)
DE (1) DE3784984T2 (de)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3826582A1 (de) * 1988-08-04 1990-02-08 Siemens Ag Verfahren zur einbettung und stufenabflachung von strukturierten oberflaechen
JP2734027B2 (ja) * 1988-11-25 1998-03-30 ソニー株式会社 配線形成方法
GB9219267D0 (en) * 1992-09-11 1992-10-28 Inmos Ltd Manufacture of semiconductor devices
GB9219281D0 (en) * 1992-09-11 1992-10-28 Inmos Ltd Manufacture of semiconductor devices

Also Published As

Publication number Publication date
AU7620687A (en) 1988-02-04
DE3784984T2 (de) 1993-10-14
EP0256917B1 (de) 1993-03-24
JPS63100745A (ja) 1988-05-02
ATE87396T1 (de) 1993-04-15
KR880002250A (ko) 1988-04-30
CA1269285A (en) 1990-05-22
EP0256917A1 (de) 1988-02-24
KR960008522B1 (en) 1996-06-26

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee