DE3783631T2 - Pseudo-statisches speicheruntersystem. - Google Patents

Pseudo-statisches speicheruntersystem.

Info

Publication number
DE3783631T2
DE3783631T2 DE8787104594T DE3783631T DE3783631T2 DE 3783631 T2 DE3783631 T2 DE 3783631T2 DE 8787104594 T DE8787104594 T DE 8787104594T DE 3783631 T DE3783631 T DE 3783631T DE 3783631 T2 DE3783631 T2 DE 3783631T2
Authority
DE
Germany
Prior art keywords
storage subsystem
static storage
pseudo static
pseudo
subsystem
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8787104594T
Other languages
English (en)
Other versions
DE3783631D1 (de
Inventor
Michael R Hereth
Patricia A Martin
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Spotware Technologies Inc
Original Assignee
Wang Laboratories Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Wang Laboratories Inc filed Critical Wang Laboratories Inc
Application granted granted Critical
Publication of DE3783631D1 publication Critical patent/DE3783631D1/de
Publication of DE3783631T2 publication Critical patent/DE3783631T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
DE8787104594T 1986-03-31 1987-03-27 Pseudo-statisches speicheruntersystem. Expired - Fee Related DE3783631T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/846,328 US4710903A (en) 1986-03-31 1986-03-31 Pseudo-static memory subsystem

Publications (2)

Publication Number Publication Date
DE3783631D1 DE3783631D1 (de) 1993-03-04
DE3783631T2 true DE3783631T2 (de) 1993-08-05

Family

ID=25297577

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8787104594T Expired - Fee Related DE3783631T2 (de) 1986-03-31 1987-03-27 Pseudo-statisches speicheruntersystem.

Country Status (6)

Country Link
US (1) US4710903A (de)
EP (1) EP0239951B1 (de)
JP (1) JP2557057B2 (de)
AU (1) AU582485B2 (de)
CA (1) CA1275150A (de)
DE (1) DE3783631T2 (de)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10058966A1 (de) * 2000-11-28 2002-06-13 Infineon Technologies Ag Verfahren zum Aufladen von Speicherzellen und Speicherbausteinen

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US5241680A (en) * 1989-06-12 1993-08-31 Grid Systems Corporation Low-power, standby mode computer
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US5404543A (en) * 1992-05-29 1995-04-04 International Business Machines Corporation Method and system for reducing an amount of power utilized by selecting a lowest power mode from a plurality of power modes
US5737566A (en) * 1993-12-20 1998-04-07 Motorola, Inc. Data processing system having a memory with both a high speed operating mode and a low power operating mode and method therefor
US5781702A (en) * 1995-06-07 1998-07-14 Univ South Western Hybrid chip-set architecture for artificial neural network system
US5566121A (en) * 1995-08-30 1996-10-15 International Business Machines Corporation Method for PCMCIA card function using DRAM technology
US5615328A (en) * 1995-08-30 1997-03-25 International Business Machines Corporation PCMCIA SRAM card function using DRAM technology
JP3625955B2 (ja) * 1996-04-16 2005-03-02 沖電気工業株式会社 画像用半導体メモリ回路
US5991851A (en) * 1997-05-02 1999-11-23 Enhanced Memory Systems, Inc. Enhanced signal processing random access memory device utilizing a DRAM memory array integrated with an associated SRAM cache and internal refresh control
US6154821A (en) * 1998-03-10 2000-11-28 Rambus Inc. Method and apparatus for initializing dynamic random access memory (DRAM) devices by levelizing a read domain
US6118719A (en) * 1998-05-20 2000-09-12 International Business Machines Corporation Self-initiated self-refresh mode for memory modules
US6334167B1 (en) 1998-08-31 2001-12-25 International Business Machines Corporation System and method for memory self-timed refresh for reduced power consumption
US6330639B1 (en) 1999-06-29 2001-12-11 Intel Corporation Method and apparatus for dynamically changing the sizes of pools that control the power consumption levels of memory devices
JP3881477B2 (ja) 1999-09-06 2007-02-14 沖電気工業株式会社 シリアルアクセスメモリ
US6243315B1 (en) * 1999-12-31 2001-06-05 James B. Goodman Computer memory system with a low power down mode
US6618791B1 (en) * 2000-09-29 2003-09-09 Intel Corporation System and method for controlling power states of a memory device via detection of a chip select signal
US7200711B2 (en) * 2002-08-15 2007-04-03 Network Appliance, Inc. Apparatus and method for placing memory into self-refresh state
US7609567B2 (en) 2005-06-24 2009-10-27 Metaram, Inc. System and method for simulating an aspect of a memory circuit
US9542352B2 (en) 2006-02-09 2017-01-10 Google Inc. System and method for reducing command scheduling constraints of memory circuits
US7472220B2 (en) 2006-07-31 2008-12-30 Metaram, Inc. Interface circuit system and method for performing power management operations utilizing power management signals
US20080082763A1 (en) 2006-10-02 2008-04-03 Metaram, Inc. Apparatus and method for power management of memory circuits by a system or component thereof
US7580312B2 (en) 2006-07-31 2009-08-25 Metaram, Inc. Power saving system and method for use with a plurality of memory circuits
US7590796B2 (en) 2006-07-31 2009-09-15 Metaram, Inc. System and method for power management in memory systems
US8130560B1 (en) 2006-11-13 2012-03-06 Google Inc. Multi-rank partial width memory modules
US9507739B2 (en) 2005-06-24 2016-11-29 Google Inc. Configurable memory circuit system and method
US8335894B1 (en) 2008-07-25 2012-12-18 Google Inc. Configurable memory system with interface circuit
US7392338B2 (en) 2006-07-31 2008-06-24 Metaram, Inc. Interface circuit system and method for autonomously performing power management operations in conjunction with a plurality of memory circuits
US8090897B2 (en) 2006-07-31 2012-01-03 Google Inc. System and method for simulating an aspect of a memory circuit
US8438328B2 (en) 2008-02-21 2013-05-07 Google Inc. Emulation of abstracted DIMMs using abstracted DRAMs
US8386722B1 (en) 2008-06-23 2013-02-26 Google Inc. Stacked DIMM memory interface
US8060774B2 (en) 2005-06-24 2011-11-15 Google Inc. Memory systems and memory modules
US10013371B2 (en) 2005-06-24 2018-07-03 Google Llc Configurable memory circuit system and method
US8089795B2 (en) 2006-02-09 2012-01-03 Google Inc. Memory module with memory stack and interface with enhanced capabilities
KR101318116B1 (ko) 2005-06-24 2013-11-14 구글 인코포레이티드 집적 메모리 코어 및 메모리 인터페이스 회로
US8077535B2 (en) 2006-07-31 2011-12-13 Google Inc. Memory refresh apparatus and method
US8359187B2 (en) 2005-06-24 2013-01-22 Google Inc. Simulating a different number of memory circuit devices
US8041881B2 (en) 2006-07-31 2011-10-18 Google Inc. Memory device with emulated characteristics
US7386656B2 (en) 2006-07-31 2008-06-10 Metaram, Inc. Interface circuit system and method for performing power management operations in conjunction with only a portion of a memory circuit
US8796830B1 (en) 2006-09-01 2014-08-05 Google Inc. Stackable low-profile lead frame package
US8055833B2 (en) 2006-10-05 2011-11-08 Google Inc. System and method for increasing capacity, performance, and flexibility of flash storage
US9171585B2 (en) 2005-06-24 2015-10-27 Google Inc. Configurable memory circuit system and method
US8244971B2 (en) 2006-07-31 2012-08-14 Google Inc. Memory circuit system and method
US8327104B2 (en) 2006-07-31 2012-12-04 Google Inc. Adjusting the timing of signals associated with a memory system
US8111566B1 (en) 2007-11-16 2012-02-07 Google, Inc. Optimal channel design for memory devices for providing a high-speed memory interface
US20080028136A1 (en) 2006-07-31 2008-01-31 Schakel Keith R Method and apparatus for refresh management of memory modules
US8397013B1 (en) 2006-10-05 2013-03-12 Google Inc. Hybrid memory module
US8081474B1 (en) 2007-12-18 2011-12-20 Google Inc. Embossed heat spreader
WO2007028109A2 (en) 2005-09-02 2007-03-08 Metaram, Inc. Methods and apparatus of stacking drams
US9632929B2 (en) 2006-02-09 2017-04-25 Google Inc. Translating an address associated with a command communicated between a system and memory circuits
US7724589B2 (en) 2006-07-31 2010-05-25 Google Inc. System and method for delaying a signal communicated from a system to at least one of a plurality of memory circuits
US8209479B2 (en) 2007-07-18 2012-06-26 Google Inc. Memory circuit system and method
US8080874B1 (en) 2007-09-14 2011-12-20 Google Inc. Providing additional space between an integrated circuit and a circuit board for positioning a component therebetween
EP2441007A1 (de) 2009-06-09 2012-04-18 Google, Inc. Programmierung von dimm-abschlusswiderstandswerten
JP6709825B2 (ja) 2018-06-14 2020-06-17 華邦電子股▲ふん▼有限公司Ｗｉｎｂｏｎｄ Ｅｌｅｃｔｒｏｎｉｃｓ Ｃｏｒｐ． Ｄｒａｍ及びその操作方法

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US4556961A (en) * 1981-05-26 1985-12-03 Tokyo Shibaura Denki Kabushiki Kaisha Semiconductor memory with delay means to reduce peak currents
JPH0632217B2 (ja) * 1981-06-29 1994-04-27 富士通株式会社 半導体記憶装置
US4725945A (en) * 1984-09-18 1988-02-16 International Business Machines Corp. Distributed cache in dynamic rams

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10058966A1 (de) * 2000-11-28 2002-06-13 Infineon Technologies Ag Verfahren zum Aufladen von Speicherzellen und Speicherbausteinen

Also Published As

Publication number Publication date
EP0239951B1 (de) 1993-01-20
EP0239951A2 (de) 1987-10-07
EP0239951A3 (en) 1990-10-24
CA1275150A (en) 1990-10-09
JPS62232798A (ja) 1987-10-13
AU6712787A (en) 1987-10-08
JP2557057B2 (ja) 1996-11-27
DE3783631D1 (de) 1993-03-04
AU582485B2 (en) 1989-03-23
US4710903A (en) 1987-12-01

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: WANG LABORATORIES, INC., BILLERICA, MASS., US

8327 Change in the person/name/address of the patent owner

Owner name: SPOTWARE TECHNOLOGIES,INC., SAN DIEGO, CALIF., US

8339 Ceased/non-payment of the annual fee