DE3783436T2 - Transistor-transistor-logikschaltung mit internen verzoegerungsgliedern. - Google Patents

Transistor-transistor-logikschaltung mit internen verzoegerungsgliedern.

Info

Publication number
DE3783436T2
DE3783436T2 DE8787309629T DE3783436T DE3783436T2 DE 3783436 T2 DE3783436 T2 DE 3783436T2 DE 8787309629 T DE8787309629 T DE 8787309629T DE 3783436 T DE3783436 T DE 3783436T DE 3783436 T2 DE3783436 T2 DE 3783436T2
Authority
DE
Germany
Prior art keywords
transistor
logic circuit
internal delay
delay links
transistor logic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8787309629T
Other languages
English (en)
Other versions
DE3783436D1 (de
Inventor
Katsuji Hirochi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of DE3783436D1 publication Critical patent/DE3783436D1/de
Application granted granted Critical
Publication of DE3783436T2 publication Critical patent/DE3783436T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/082—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using bipolar transistors
    • H03K19/088—Transistor-transistor logic
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00346—Modifications for eliminating interference or parasitic voltages or currents
    • H03K19/00353—Modifications for eliminating interference or parasitic voltages or currents in bipolar transistor circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Power Engineering (AREA)
  • Logic Circuits (AREA)
  • Electronic Switches (AREA)
  • Pulse Circuits (AREA)
DE8787309629T 1986-10-31 1987-10-30 Transistor-transistor-logikschaltung mit internen verzoegerungsgliedern. Expired - Fee Related DE3783436T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61260942A JPS63115419A (ja) 1986-10-31 1986-10-31 Ｔｔｌ回路

Publications (2)

Publication Number Publication Date
DE3783436D1 DE3783436D1 (de) 1993-02-18
DE3783436T2 true DE3783436T2 (de) 1993-05-06

Family

ID=17354919

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8787309629T Expired - Fee Related DE3783436T2 (de) 1986-10-31 1987-10-30 Transistor-transistor-logikschaltung mit internen verzoegerungsgliedern.

Country Status (5)

Country Link
US (1) US4803383A (de)
EP (1) EP0266218B1 (de)
JP (1) JPS63115419A (de)
KR (1) KR900008024B1 (de)
DE (1) DE3783436T2 (de)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01119773A (ja) * 1987-11-02 1989-05-11 Mitsubishi Electric Corp インバータ回路
JP2724872B2 (ja) * 1989-04-12 1998-03-09 三菱電機株式会社 半導体集積回路用入力回路
US5039881A (en) * 1989-06-23 1991-08-13 Motorola, Inc. High speed, low power input buffer
US4987318A (en) * 1989-09-18 1991-01-22 International Business Machines Corporation High level clamp driver for wire-or buses
JPH03222516A (ja) * 1990-01-29 1991-10-01 Fujitsu Ltd 半導体装置

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4394588A (en) * 1980-12-30 1983-07-19 International Business Machines Corporation Controllable di/dt push/pull driver
US4581550A (en) * 1984-03-06 1986-04-08 Fairchild Camera & Instrument Corporation TTL tristate device with reduced output capacitance
US4661727A (en) * 1984-07-19 1987-04-28 Fairchild Semiconductor Corporation Multiple phase-splitter TTL output circuit with improved drive characteristics
JPS61150519A (ja) * 1984-12-25 1986-07-09 Nec Corp 半導体集積論理回路
US4698525A (en) * 1985-12-03 1987-10-06 Monolithic Memories, Inc. Buffered Miller current compensating circuit
US4697103A (en) * 1986-03-10 1987-09-29 Quadic Systems, Inc. Low power high current sinking TTL circuit

Also Published As

Publication number Publication date
EP0266218B1 (de) 1993-01-07
DE3783436D1 (de) 1993-02-18
KR880005755A (ko) 1988-06-30
KR900008024B1 (en) 1990-10-29
EP0266218A2 (de) 1988-05-04
JPS63115419A (ja) 1988-05-20
JPH0515325B2 (de) 1993-03-01
EP0266218A3 (en) 1989-08-23
US4803383A (en) 1989-02-07

Similar Documents

Publication Publication Date Title
DE68920083D1 (de) Hochschaltlogik.
DE68917235D1 (de) Programmierbare logische Schaltung.
DE3786247T2 (de) Lanzette mit rueckfuehrung.
DE3880900D1 (de) Bauelement mit vorgefertigten waenden.
DE3776462D1 (de) Keilriemen mit querkoerpern.
DE3888863T2 (de) BIFET-Logik-Schaltung.
DE3788242D1 (de) Binäre logische Schaltung.
DE3872184D1 (de) Logikanalysator.
DE3779784D1 (de) Logische schaltung.
DE3778760D1 (de) Kopierer mit selektiver ausgabe.
DE69023817D1 (de) Verzögerungsschaltung mit stabiler Verzögerungszeit.
DE3879333T2 (de) Halbleiteranordnung mit mehrschichtleiter.
DE3688564T2 (de) Sequentielle logische Schaltung.
DE3785833D1 (de) Logikschaltung.
DE68901985T2 (de) Verzoegerungsschaltung.
IT8420827A0 (it) Catena con maglie ad elevata resistenza.
DE3685356D1 (de) Tri-state-pufferschaltung.
DE3854012D1 (de) Fehlertolerante Logikschaltung.
NL188672C (nl) Drie-toestanden complementair mos-ic.
DE3783436T2 (de) Transistor-transistor-logikschaltung mit internen verzoegerungsgliedern.
DE3485323D1 (de) Addierschaltung mit uebertragungskette des vorladungstyps.
DE3880024D1 (de) Ecl/nmos-pegelwandler.
DE68916612D1 (de) ECL/CMOS-Pegelwandler.
DE68914583D1 (de) Integrierte Schaltung mit Ausgangsschaltung.
DE3782992T2 (de) Verzoegerungsleitung mit allpass-kreisen.

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee