DE3743591A1 - Verfahren zum herstellen einer halbleiteranordnung - Google Patents

Verfahren zum herstellen einer halbleiteranordnung

Info

Publication number
DE3743591A1
DE3743591A1 DE19873743591 DE3743591A DE3743591A1 DE 3743591 A1 DE3743591 A1 DE 3743591A1 DE 19873743591 DE19873743591 DE 19873743591 DE 3743591 A DE3743591 A DE 3743591A DE 3743591 A1 DE3743591 A1 DE 3743591A1
Authority
DE
Germany
Prior art keywords
layer
titanium
titanium nitride
semiconductor
nitride layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
DE19873743591
Other languages
German (de)
English (en)
Other versions
DE3743591C2 (https=
Inventor
Hajime Arai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Publication of DE3743591A1 publication Critical patent/DE3743591A1/de
Application granted granted Critical
Publication of DE3743591C2 publication Critical patent/DE3743591C2/de
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/047—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers by introducing additional elements therein
    • H10W20/048—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers by introducing additional elements therein by using plasmas or gaseous environments, e.g. by nitriding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H10D64/0111—Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors
    • H10D64/0112—Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors using conductive layers comprising silicides
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H10D64/0111—Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors
    • H10D64/0112—Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors using conductive layers comprising silicides
    • H10D64/01125—Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors using conductive layers comprising silicides the silicides being formed by chemical reaction with the semiconductor after the contact hole formation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/033—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/047—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers by introducing additional elements therein
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/425—Barrier, adhesion or liner layers

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
DE19873743591 1986-12-24 1987-12-22 Verfahren zum herstellen einer halbleiteranordnung Granted DE3743591A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61309838A JPS63160328A (ja) 1986-12-24 1986-12-24 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
DE3743591A1 true DE3743591A1 (de) 1988-07-07
DE3743591C2 DE3743591C2 (https=) 1992-12-17

Family

ID=17997879

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19873743591 Granted DE3743591A1 (de) 1986-12-24 1987-12-22 Verfahren zum herstellen einer halbleiteranordnung

Country Status (3)

Country Link
JP (1) JPS63160328A (https=)
KR (1) KR910002452B1 (https=)
DE (1) DE3743591A1 (https=)

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3930655A1 (de) * 1988-09-13 1990-03-22 Mitsubishi Electric Corp Halbleitervorrichtung mit vielschichtig gestapelter verbindungsschicht und verfahren zu deren herstellung
EP0377245A1 (en) * 1989-01-04 1990-07-11 Koninklijke Philips Electronics N.V. Semiconductor device and method of manufacturing a semiconductor device
EP0506129A1 (en) * 1991-03-29 1992-09-30 Applied Materials, Inc. Process for forming an electrical contact through an insulation layer to a silicon semiconductor wafer thereunder
EP0452921A3 (en) * 1990-04-20 1992-10-28 Applied Materials Inc. Formation of titanium nitride on semiconductor wafer by reaction of titanium with nitrogen-bearing gas in an integrated processing system
EP0697729A3 (en) * 1994-08-18 1996-11-13 Oki Electric Ind Co Ltd Contact structure with metallic barrier layer and manufacturing process
US5877087A (en) * 1995-11-21 1999-03-02 Applied Materials, Inc. Low temperature integrated metallization process and apparatus
US5877086A (en) * 1996-07-12 1999-03-02 Applied Materials, Inc. Metal planarization using a CVD wetting film
US6001420A (en) * 1996-09-23 1999-12-14 Applied Materials, Inc. Semi-selective chemical vapor deposition
US6066358A (en) * 1995-11-21 2000-05-23 Applied Materials, Inc. Blanket-selective chemical vapor deposition using an ultra-thin nucleation layer
US6110828A (en) * 1996-12-30 2000-08-29 Applied Materials, Inc. In-situ capped aluminum plug (CAP) process using selective CVD AL for integrated plug/interconnect metallization
US6139905A (en) * 1997-04-11 2000-10-31 Applied Materials, Inc. Integrated CVD/PVD Al planarization using ultra-thin nucleation layers
US6537905B1 (en) 1996-12-30 2003-03-25 Applied Materials, Inc. Fully planarized dual damascene metallization using copper line interconnect and selective CVD aluminum plug
US6605531B1 (en) 1997-11-26 2003-08-12 Applied Materials, Inc. Hole-filling technique using CVD aluminum and PVD aluminum integration
US6797620B2 (en) 2002-04-16 2004-09-28 Applied Materials, Inc. Method and apparatus for improved electroplating fill of an aperture

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR920008842B1 (ko) * 1988-07-11 1992-10-09 삼성전자 주식회사 반도체장치의 금속배선막 도포방법
JP2720567B2 (ja) * 1990-03-28 1998-03-04 ソニー株式会社 半導体装置の製造方法
GB2242781A (en) * 1990-04-06 1991-10-09 Koninkl Philips Electronics Nv A semiconductor device
KR100510465B1 (ko) * 1998-05-12 2005-10-24 삼성전자주식회사 반도체장치의 배리어 금속막 형성방법

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3140669A1 (de) * 1981-10-13 1983-04-28 Siemens AG, 1000 Berlin und 8000 München Verfahren zum herstellen von halbleitervorrichtungen

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3140669A1 (de) * 1981-10-13 1983-04-28 Siemens AG, 1000 Berlin und 8000 München Verfahren zum herstellen von halbleitervorrichtungen

Non-Patent Citations (7)

* Cited by examiner, † Cited by third party
Title
Maeda, T. et. al.: Effects of Ti Interlevel Existence in Al/Ti/TiN/Ti Structure for Highly Reliable Interconnection. In: VLSI Symposium 1985, Dig. Tech. Papers, V-7, S. 50-51 *
Maeda, T. et.al.: Highly Reliable One-Micron-Rule Interconnection Utilizing TiN Barrier Metal. In: IEDM 85, 1985, S. 610-613 *
Murarka, S.P.: Silicides for VLSI Applications Academic Press, 1983, New York, S. 115-131 und 164-170 *
Patent Abstract zur JP-A2 60-176231 (A) *
Patent Abstract zur JP-A2 60-193333 (A) *
Patent Abstract zur JP-A2 61-114524 (A) *
Patent Abstract zur JP-A2 61-142739 (A) *

Cited By (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3930655A1 (de) * 1988-09-13 1990-03-22 Mitsubishi Electric Corp Halbleitervorrichtung mit vielschichtig gestapelter verbindungsschicht und verfahren zu deren herstellung
EP0377245A1 (en) * 1989-01-04 1990-07-11 Koninklijke Philips Electronics N.V. Semiconductor device and method of manufacturing a semiconductor device
EP0452921A3 (en) * 1990-04-20 1992-10-28 Applied Materials Inc. Formation of titanium nitride on semiconductor wafer by reaction of titanium with nitrogen-bearing gas in an integrated processing system
EP0506129A1 (en) * 1991-03-29 1992-09-30 Applied Materials, Inc. Process for forming an electrical contact through an insulation layer to a silicon semiconductor wafer thereunder
US5920122A (en) * 1994-08-18 1999-07-06 Oki Electric Industry Co., Ltd. Contact structure using barrier metal and method of manufacturing the same
EP0697729A3 (en) * 1994-08-18 1996-11-13 Oki Electric Ind Co Ltd Contact structure with metallic barrier layer and manufacturing process
US5654235A (en) * 1994-08-18 1997-08-05 Oki Electric Industry Co., Ltd. Method of manufacturing contact structure using barrier metal
US5877087A (en) * 1995-11-21 1999-03-02 Applied Materials, Inc. Low temperature integrated metallization process and apparatus
US6066358A (en) * 1995-11-21 2000-05-23 Applied Materials, Inc. Blanket-selective chemical vapor deposition using an ultra-thin nucleation layer
US6743714B2 (en) 1995-11-21 2004-06-01 Applied Materials, Inc. Low temperature integrated metallization process and apparatus
US5877086A (en) * 1996-07-12 1999-03-02 Applied Materials, Inc. Metal planarization using a CVD wetting film
US6430458B1 (en) 1996-09-23 2002-08-06 Applied Materials, Inc. Semi-selective chemical vapor deposition
US6001420A (en) * 1996-09-23 1999-12-14 Applied Materials, Inc. Semi-selective chemical vapor deposition
US6110828A (en) * 1996-12-30 2000-08-29 Applied Materials, Inc. In-situ capped aluminum plug (CAP) process using selective CVD AL for integrated plug/interconnect metallization
US6537905B1 (en) 1996-12-30 2003-03-25 Applied Materials, Inc. Fully planarized dual damascene metallization using copper line interconnect and selective CVD aluminum plug
US7112528B2 (en) 1996-12-30 2006-09-26 Applied Materials, Inc. Fully planarized dual damascene metallization using copper line interconnect and selective CVD aluminum plug
US6139905A (en) * 1997-04-11 2000-10-31 Applied Materials, Inc. Integrated CVD/PVD Al planarization using ultra-thin nucleation layers
US6605531B1 (en) 1997-11-26 2003-08-12 Applied Materials, Inc. Hole-filling technique using CVD aluminum and PVD aluminum integration
US6797620B2 (en) 2002-04-16 2004-09-28 Applied Materials, Inc. Method and apparatus for improved electroplating fill of an aperture

Also Published As

Publication number Publication date
KR880008418A (ko) 1988-08-31
JPS63160328A (ja) 1988-07-04
KR910002452B1 (ko) 1991-04-22
DE3743591C2 (https=) 1992-12-17

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Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
D2 Grant after examination
8364 No opposition during term of opposition
8320 Willingness to grant licences declared (paragraph 23)
8339 Ceased/non-payment of the annual fee