DE3685906D1 - Hochtemperatur abhebeverfahren ohne zwischenschicht fuer eine strukturierte zwischenverbindungsschicht. - Google Patents
Hochtemperatur abhebeverfahren ohne zwischenschicht fuer eine strukturierte zwischenverbindungsschicht.Info
- Publication number
- DE3685906D1 DE3685906D1 DE8686105142T DE3685906T DE3685906D1 DE 3685906 D1 DE3685906 D1 DE 3685906D1 DE 8686105142 T DE8686105142 T DE 8686105142T DE 3685906 T DE3685906 T DE 3685906T DE 3685906 D1 DE3685906 D1 DE 3685906D1
- Authority
- DE
- Germany
- Prior art keywords
- interlayer
- high temperature
- structured
- lifting method
- temperature lifting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000011229 interlayer Substances 0.000 title 2
- 239000010410 layer Substances 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/7688—Filling of holes, grooves or trenches, e.g. vias, with conductive material by deposition over sacrificial masking layer, e.g. lift-off
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0272—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers for lift-off processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31127—Etching organic layers
- H01L21/31133—Etching organic layers by chemical means
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/14—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using spraying techniques to apply the conductive material, e.g. vapour evaporation
- H05K3/143—Masks therefor
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/942—Masking
- Y10S438/948—Radiation resist
- Y10S438/951—Lift-off
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Drying Of Semiconductors (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US06/728,072 US4606998A (en) | 1985-04-30 | 1985-04-30 | Barrierless high-temperature lift-off process |
Publications (2)
Publication Number | Publication Date |
---|---|
DE3685906D1 true DE3685906D1 (de) | 1992-08-13 |
DE3685906T2 DE3685906T2 (de) | 1993-02-04 |
Family
ID=24925304
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE8686105142T Expired - Fee Related DE3685906T2 (de) | 1985-04-30 | 1986-04-15 | Hochtemperatur abhebeverfahren ohne zwischenschicht fuer eine strukturierte zwischenverbindungsschicht. |
Country Status (5)
Country | Link |
---|---|
US (1) | US4606998A (de) |
EP (1) | EP0200082B1 (de) |
JP (1) | JPS61252648A (de) |
CA (1) | CA1223089A (de) |
DE (1) | DE3685906T2 (de) |
Families Citing this family (42)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
IT1184535B (it) * | 1985-05-03 | 1987-10-28 | Gte Telecom Spa | Processo di ricavo di linee in film sottile |
US4828964A (en) * | 1985-08-20 | 1989-05-09 | International Business Machines Corporation | Polyimide formulation for forming a patterned film on a substrate |
US4890157A (en) * | 1986-01-31 | 1989-12-26 | Texas Instruments Incorporated | Integrated circuit product having a polyimide film interconnection structure |
ZA87922B (en) * | 1986-02-28 | 1987-09-30 | Macdermid Inc | Photoresist stripper composition |
US4943471A (en) * | 1986-05-20 | 1990-07-24 | Kanegafuchi Kagaku Kogyo Kabushiki Kaisha | Patterned thin film and process for preparing the same |
US4886573A (en) * | 1986-08-27 | 1989-12-12 | Hitachi, Ltd. | Process for forming wiring on substrate |
GB2212979A (en) * | 1987-12-02 | 1989-08-02 | Philips Nv | Fabricating electrical connections,particularly in integrated circuit manufacture |
US4846929A (en) * | 1988-07-13 | 1989-07-11 | Ibm Corporation | Wet etching of thermally or chemically cured polyimide |
GB2226991A (en) * | 1989-01-13 | 1990-07-18 | Ibm | Etching organic polymeric materials |
US4911786A (en) * | 1989-04-26 | 1990-03-27 | International Business Machines Corporation | Method of etching polyimides and resulting passivation structure |
US4961259A (en) * | 1989-06-16 | 1990-10-09 | Hughes Aircraft Company | Method of forming an interconnection by an excimer laser |
US5006488A (en) * | 1989-10-06 | 1991-04-09 | International Business Machines Corporation | High temperature lift-off process |
SE465193B (sv) * | 1989-12-06 | 1991-08-05 | Ericsson Telefon Ab L M | Foer hoegspaenning avsedd ic-krets |
US5130229A (en) * | 1990-04-26 | 1992-07-14 | International Business Machines Corporation | Multi layer thin film wiring process featuring self-alignment of vias |
DE4034868C2 (de) * | 1990-11-02 | 1995-02-16 | Itt Ind Gmbh Deutsche | Verfahren zur selektiven Metallabscheidung bei der Herstellung von Halbleiterbauelementen |
DE69219998T2 (de) * | 1991-10-31 | 1997-12-18 | Sgs Thomson Microelectronics | Verfahren zur Entfernung von Polymeren aus Sacklöchern in Halbleitervorrichtungen |
US5242864A (en) * | 1992-06-05 | 1993-09-07 | Intel Corporation | Polyimide process for protecting integrated circuits |
DE69330603T2 (de) * | 1993-09-30 | 2002-07-04 | Consorzio Per La Ricerca Sulla Microelettronica Nel Mezzogiorno, Catania | Verfahren zur Metallisierung und Verbindung bei der Herstellung von Leistungshalbleiterbauelementen |
DE69321965T2 (de) * | 1993-12-24 | 1999-06-02 | Consorzio Per La Ricerca Sulla Microelettronica Nel Mezzogiorno, Catania | MOS-Leistungs-Chip-Typ und Packungszusammenbau |
US5798287A (en) * | 1993-12-24 | 1998-08-25 | Consorzio Per La Ricerca Sulla Microelettronica Nel Mezzogiorno | Method for forming a power MOS device chip |
EP0660402B1 (de) * | 1993-12-24 | 1998-11-04 | Consorzio per la Ricerca sulla Microelettronica nel Mezzogiorno | Leistungs-Halbleiterbauelement |
US5597983A (en) * | 1994-02-03 | 1997-01-28 | Sgs-Thomson Microelectronics, Inc. | Process of removing polymers in semiconductor vias |
US5503961A (en) * | 1994-11-02 | 1996-04-02 | International Business Machines Corporation | Process for forming multilayer lift-off structures |
US5474956A (en) * | 1995-03-14 | 1995-12-12 | Hughes Aircraft Company | Method of fabricating metallized substrates using an organic etch block layer |
JP2817664B2 (ja) * | 1995-04-24 | 1998-10-30 | 日本電気株式会社 | 半導体装置の製造方法 |
US6410922B1 (en) | 1995-11-29 | 2002-06-25 | Konstantinos Evangelos Spartiotis | Forming contacts on semiconductor substrates for radiation detectors and imaging devices |
GB2352084B (en) * | 1999-07-13 | 2002-11-13 | Simage Oy | Forming contacts on semiconductor substrates for radiation detectors and imaging devices |
US6136689A (en) * | 1998-08-14 | 2000-10-24 | Micron Technology, Inc. | Method of forming a micro solder ball for use in C4 bonding process |
US6998711B1 (en) * | 1998-08-14 | 2006-02-14 | Micron Technology, Inc. | Method of forming a micro solder ball for use in C4 bonding process |
US6589712B1 (en) * | 1998-11-04 | 2003-07-08 | Yi-Ren Hsu | Method for forming a passivation layer using polyimide layer as a mask |
US6878396B2 (en) * | 2000-04-10 | 2005-04-12 | Micron Technology, Inc. | Micro C-4 semiconductor die and method for depositing connection sites thereon |
US6759275B1 (en) * | 2001-09-04 | 2004-07-06 | Megic Corporation | Method for making high-performance RF integrated circuits |
JP4085384B2 (ja) * | 2003-06-09 | 2008-05-14 | ミネベア株式会社 | 薄膜パターンの形成方法 |
DE102005002550B4 (de) * | 2005-01-19 | 2007-02-08 | Infineon Technologies Ag | Lift-Off-Verfahren |
US7553718B2 (en) * | 2005-01-28 | 2009-06-30 | Texas Instruments Incorporated | Methods, systems and structures for forming semiconductor structures incorporating high-temperature processing steps |
CN1901163B (zh) | 2005-07-22 | 2011-04-13 | 米辑电子股份有限公司 | 连续电镀制作线路组件的方法及线路组件结构 |
KR100633994B1 (ko) * | 2005-07-26 | 2006-10-13 | 동부일렉트로닉스 주식회사 | 반도체 소자의 웰 포토레지스트 패턴 및 그 형성 방법 |
US20070036890A1 (en) * | 2005-08-12 | 2007-02-15 | Feng Zhong | Method of making a fuel cell component using a mask |
CN101501832A (zh) * | 2006-08-10 | 2009-08-05 | 皇家飞利浦电子股份有限公司 | 具有塑料基底的有源矩阵显示器和其他电子器件 |
US7862987B2 (en) * | 2007-11-20 | 2011-01-04 | International Business Machines Corporation | Method for forming an electrical structure comprising multiple photosensitive materials |
CN110098108A (zh) * | 2018-01-31 | 2019-08-06 | 苏州锐材半导体有限公司 | 一种聚酰亚胺微掩膜的制作方法 |
US11304303B2 (en) * | 2020-04-30 | 2022-04-12 | Dujud Llc | Methods and processes for forming electrical circuitries on three-dimensional geometries |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3985597A (en) * | 1975-05-01 | 1976-10-12 | International Business Machines Corporation | Process for forming passivated metal interconnection system with a planar surface |
JPS55163860A (en) * | 1979-06-06 | 1980-12-20 | Toshiba Corp | Manufacture of semiconductor device |
US4377115A (en) * | 1979-12-21 | 1983-03-22 | Kolze Bruce A | Furnace for burning particulate wood waste material |
US4353778A (en) * | 1981-09-04 | 1982-10-12 | International Business Machines Corporation | Method of etching polyimide |
US4428796A (en) * | 1982-08-02 | 1984-01-31 | Fairchild Camera And Instrument Corporation | Adhesion bond-breaking of lift-off regions on semiconductor structures |
US4451971A (en) * | 1982-08-02 | 1984-06-05 | Fairchild Camera And Instrument Corporation | Lift-off wafer processing |
JPS6018923A (ja) * | 1983-07-13 | 1985-01-31 | Hitachi Ltd | ポリイミド系樹脂層のテ−パエツチング方法 |
US4523976A (en) * | 1984-07-02 | 1985-06-18 | Motorola, Inc. | Method for forming semiconductor devices |
US4624740A (en) * | 1985-01-22 | 1986-11-25 | International Business Machines Corporation | Tailoring of via-hole sidewall slope |
-
1985
- 1985-04-30 US US06/728,072 patent/US4606998A/en not_active Expired - Lifetime
- 1985-11-19 CA CA000495660A patent/CA1223089A/en not_active Expired
-
1986
- 1986-01-29 JP JP61015985A patent/JPS61252648A/ja active Pending
- 1986-04-15 DE DE8686105142T patent/DE3685906T2/de not_active Expired - Fee Related
- 1986-04-15 EP EP86105142A patent/EP0200082B1/de not_active Expired
Also Published As
Publication number | Publication date |
---|---|
EP0200082A3 (en) | 1988-11-17 |
JPS61252648A (ja) | 1986-11-10 |
CA1223089A (en) | 1987-06-16 |
EP0200082B1 (de) | 1992-07-08 |
US4606998A (en) | 1986-08-19 |
EP0200082A2 (de) | 1986-11-05 |
DE3685906T2 (de) | 1993-02-04 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |