DE3586554D1 - Verfahren zur selektiven exposition der seitenwaende eines grabens und dessen verwendung fuer die herstellung von einem substratkontakt aus metallsiliziden mit dielektrischem material gefuellten graeben isolierter anordnungen. - Google Patents

Verfahren zur selektiven exposition der seitenwaende eines grabens und dessen verwendung fuer die herstellung von einem substratkontakt aus metallsiliziden mit dielektrischem material gefuellten graeben isolierter anordnungen.

Info

Publication number
DE3586554D1
DE3586554D1 DE8585106828T DE3586554T DE3586554D1 DE 3586554 D1 DE3586554 D1 DE 3586554D1 DE 8585106828 T DE8585106828 T DE 8585106828T DE 3586554 T DE3586554 T DE 3586554T DE 3586554 D1 DE3586554 D1 DE 3586554D1
Authority
DE
Germany
Prior art keywords
tranks
trench
sidewalls
insulated
arrangements
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8585106828T
Other languages
English (en)
Other versions
DE3586554T2 (de
Inventor
George Richard Goth
Thomas Adrian Hansen
James Steve Makris
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE3586554D1 publication Critical patent/DE3586554D1/de
Publication of DE3586554T2 publication Critical patent/DE3586554T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
    • H01L21/743—Making of internal connections, substrate contacts

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Drying Of Semiconductors (AREA)
  • Bipolar Transistors (AREA)
DE8585106828T 1984-06-29 1985-06-03 Verfahren zur selektiven exposition der seitenwaende eines grabens und dessen verwendung fuer die herstellung von einem substratkontakt aus metallsiliziden mit dielektrischem material gefuellten graeben isolierter anordnungen. Expired - Fee Related DE3586554T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/626,271 US4549927A (en) 1984-06-29 1984-06-29 Method of selectively exposing the sidewalls of a trench and its use to the forming of a metal silicide substrate contact for dielectric filled deep trench isolated devices

Publications (2)

Publication Number Publication Date
DE3586554D1 true DE3586554D1 (de) 1992-10-01
DE3586554T2 DE3586554T2 (de) 1993-04-08

Family

ID=24509683

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8585106828T Expired - Fee Related DE3586554T2 (de) 1984-06-29 1985-06-03 Verfahren zur selektiven exposition der seitenwaende eines grabens und dessen verwendung fuer die herstellung von einem substratkontakt aus metallsiliziden mit dielektrischem material gefuellten graeben isolierter anordnungen.

Country Status (4)

Country Link
US (1) US4549927A (de)
EP (1) EP0166983B1 (de)
JP (1) JPS6118147A (de)
DE (1) DE3586554T2 (de)

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US4589193A (en) * 1984-06-29 1986-05-20 International Business Machines Corporation Metal silicide channel stoppers for integrated circuits and method for making the same
US4890145A (en) * 1984-08-31 1989-12-26 Texas Instruments Incorporated dRAM cell and array
JPS61191043A (ja) * 1985-02-20 1986-08-25 Toshiba Corp 半導体装置
US4648173A (en) * 1985-05-28 1987-03-10 International Business Machines Corporation Fabrication of stud-defined integrated circuit structure
US4674173A (en) * 1985-06-28 1987-06-23 Texas Instruments Incorporated Method for fabricating bipolar transistor
NL8502765A (nl) * 1985-10-10 1987-05-04 Philips Nv Werkwijze ter vervaardiging van een halfgeleiderinrichting.
US4824797A (en) * 1985-10-31 1989-04-25 International Business Machines Corporation Self-aligned channel stop
US4753866A (en) * 1986-02-24 1988-06-28 Texas Instruments Incorporated Method for processing an interlevel dielectric suitable for VLSI metallization schemes
US4725562A (en) * 1986-03-27 1988-02-16 International Business Machines Corporation Method of making a contact to a trench isolated device
DE3736531A1 (de) * 1986-10-30 1988-05-11 Mitsubishi Electric Corp Verfahren zur herstellung einer halbleitereinrichtung
US4980747A (en) * 1986-12-22 1990-12-25 Texas Instruments Inc. Deep trench isolation with surface contact to substrate
DE3715232A1 (de) * 1987-05-07 1988-11-17 Siemens Ag Verfahren zur substratkontaktierung bei der herstellung von durch isolationsgraeben getrennten bipolartransistorschaltungen
US4835115A (en) * 1987-12-07 1989-05-30 Texas Instruments Incorporated Method for forming oxide-capped trench isolation
US4970689A (en) * 1988-03-07 1990-11-13 International Business Machines Corporation Charge amplifying trench memory cell
US4914740A (en) * 1988-03-07 1990-04-03 International Business Corporation Charge amplifying trench memory cell
JPH02271535A (ja) * 1988-12-28 1990-11-06 Synergy Semiconductor Corp バイポーラ構造における基板タップ及びこの製造方法
US5106777A (en) * 1989-09-27 1992-04-21 Texas Instruments Incorporated Trench isolation process with reduced topography
CH681677B5 (fr) * 1991-02-05 1993-11-15 Complications Sa Procédé d'initialisation du calendrier perpétuel d'un chronographe analogique à quartz et chronographe à quartz pour sa mise en oeuvre.
US5096849A (en) * 1991-04-29 1992-03-17 International Business Machines Corporation Process for positioning a mask within a concave semiconductor structure
US5433794A (en) * 1992-12-10 1995-07-18 Micron Technology, Inc. Spacers used to form isolation trenches with improved corners
US5455064A (en) * 1993-11-12 1995-10-03 Fujitsu Limited Process for fabricating a substrate with thin film capacitor and insulating plug
US5604159A (en) 1994-01-31 1997-02-18 Motorola, Inc. Method of making a contact structure
US5681776A (en) * 1994-03-15 1997-10-28 National Semiconductor Corporation Planar selective field oxide isolation process using SEG/ELO
US5872044A (en) * 1994-06-15 1999-02-16 Harris Corporation Late process method for trench isolation
US5668018A (en) * 1995-06-07 1997-09-16 International Business Machines Corporation Method for defining a region on a wall of a semiconductor structure
AUPN606395A0 (en) * 1995-10-19 1995-11-09 Unisearch Limited Metallization of buried contact solar cells
DE19630050B4 (de) * 1996-07-25 2005-03-10 Infineon Technologies Ag Herstellverfahren für eine Lackmaske auf einem Substrat mit einem Graben
US6479368B1 (en) * 1998-03-02 2002-11-12 Kabushiki Kaisha Toshiba Method of manufacturing a semiconductor device having a shallow trench isolating region
US6074903A (en) * 1998-06-16 2000-06-13 Siemens Aktiengesellschaft Method for forming electrical isolation for semiconductor devices
US6300666B1 (en) 1998-09-30 2001-10-09 Honeywell Inc. Method for forming a frontside contact to the silicon substrate of a SOI wafer in the presence of planarized contact dielectrics
US6100200A (en) * 1998-12-21 2000-08-08 Advanced Technology Materials, Inc. Sputtering process for the conformal deposition of a metallization or insulating layer
US6537912B1 (en) 2000-08-25 2003-03-25 Micron Technology Inc. Method of forming an encapsulated conductive pillar
US6724798B2 (en) 2001-12-31 2004-04-20 Honeywell International Inc. Optoelectronic devices and method of production
JP3967193B2 (ja) * 2002-05-21 2007-08-29 スパンション エルエルシー 不揮発性半導体記憶装置及びその製造方法
US7262089B2 (en) * 2004-03-11 2007-08-28 Micron Technology, Inc. Methods of forming semiconductor structures
EP1787327A4 (de) * 2004-06-04 2010-09-08 Newsouth Innovations Pty Ltd Dünnfilm-solarzellen-verbindung
US7002190B1 (en) * 2004-09-21 2006-02-21 International Business Machines Corporation Method of collector formation in BiCMOS technology
US7679130B2 (en) * 2005-05-10 2010-03-16 Infineon Technologies Ag Deep trench isolation structures and methods of formation thereof
US7982284B2 (en) * 2006-06-28 2011-07-19 Infineon Technologies Ag Semiconductor component including an isolation structure and a contact to the substrate
KR100853193B1 (ko) * 2007-01-08 2008-08-21 삼성전자주식회사 반도체 소자 및 그 형성방법
US7691734B2 (en) * 2007-03-01 2010-04-06 International Business Machines Corporation Deep trench based far subcollector reachthrough
US7923373B2 (en) 2007-06-04 2011-04-12 Micron Technology, Inc. Pitch multiplication using self-assembling materials
US8338265B2 (en) 2008-11-12 2012-12-25 International Business Machines Corporation Silicided trench contact to buried conductive layer
US8647945B2 (en) 2010-12-03 2014-02-11 International Business Machines Corporation Method of forming substrate contact for semiconductor on insulator (SOI) substrate
US9236326B2 (en) 2014-04-25 2016-01-12 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure and fabricating method thereof
US9324632B2 (en) 2014-05-28 2016-04-26 Globalfoundries Inc. Semiconductor structures with isolated ohmic trenches and stand-alone isolation trenches and related method
CN115382743B (zh) * 2021-05-24 2023-08-22 成宏能源股份有限公司 形成具有涂层的结构的方法及具有涂层的结构

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Publication number Priority date Publication date Assignee Title
US3381182A (en) * 1964-10-19 1968-04-30 Philco Ford Corp Microcircuits having buried conductive layers
US4118728A (en) * 1976-09-03 1978-10-03 Fairchild Camera And Instrument Corporation Integrated circuit structures utilizing conductive buried regions
US4149177A (en) * 1976-09-03 1979-04-10 Fairchild Camera And Instrument Corporation Method of fabricating conductive buried regions in integrated circuits and the resulting structures
DE2926874A1 (de) * 1979-07-03 1981-01-22 Siemens Ag Verfahren zum herstellen von niederohmigen, diffundierten bereichen bei der silizium-gate-technologie
JPS5673446A (en) * 1979-11-21 1981-06-18 Chiyou Lsi Gijutsu Kenkyu Kumiai Manufacture of semiconductor device
EP0098318B1 (de) * 1982-07-03 1987-02-11 Ibm Deutschland Gmbh Verfahren zum Herstellen von Gräben mit im wesentlichen vertikalen Seitenwänden in Silicium durch reaktives Ionenätzen
US4589193A (en) * 1984-06-29 1986-05-20 International Business Machines Corporation Metal silicide channel stoppers for integrated circuits and method for making the same
US4663832A (en) * 1984-06-29 1987-05-12 International Business Machines Corporation Method for improving the planarity and passivation in a semiconductor isolation trench arrangement

Also Published As

Publication number Publication date
EP0166983A3 (en) 1989-03-08
DE3586554T2 (de) 1993-04-08
JPS6118147A (ja) 1986-01-27
JPH0362024B2 (de) 1991-09-24
EP0166983B1 (de) 1992-08-26
US4549927A (en) 1985-10-29
EP0166983A2 (de) 1986-01-08

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Legal Events

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8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee