DE3572257D1 - Method of manufacturing aluminium contacts through a thick insulating layer in a circuit - Google Patents
Method of manufacturing aluminium contacts through a thick insulating layer in a circuitInfo
- Publication number
- DE3572257D1 DE3572257D1 DE8585400706T DE3572257T DE3572257D1 DE 3572257 D1 DE3572257 D1 DE 3572257D1 DE 8585400706 T DE8585400706 T DE 8585400706T DE 3572257 T DE3572257 T DE 3572257T DE 3572257 D1 DE3572257 D1 DE 3572257D1
- Authority
- DE
- Germany
- Prior art keywords
- circuit
- insulating layer
- thick insulating
- manufacturing aluminium
- aluminium contacts
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53214—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium
- H01L23/53223—Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR8405906A FR2563048B1 (fr) | 1984-04-13 | 1984-04-13 | Procede de realisation de contacts d'aluminium a travers une couche isolante epaisse dans un circuit integre |
Publications (1)
Publication Number | Publication Date |
---|---|
DE3572257D1 true DE3572257D1 (en) | 1989-09-14 |
Family
ID=9303163
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE8585400706T Expired DE3572257D1 (en) | 1984-04-13 | 1985-04-09 | Method of manufacturing aluminium contacts through a thick insulating layer in a circuit |
Country Status (5)
Country | Link |
---|---|
US (1) | US4592802A (de) |
EP (1) | EP0165085B1 (de) |
JP (1) | JPS60253245A (de) |
DE (1) | DE3572257D1 (de) |
FR (1) | FR2563048B1 (de) |
Families Citing this family (37)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2581666B2 (ja) * | 1985-09-06 | 1997-02-12 | 株式会社日立製作所 | 配線構造体の製造方法 |
EP0241480B1 (de) * | 1985-09-27 | 1991-10-23 | Unisys Corporation | Verfahren zur herstellung einer konischen kontaktöffnung in polyimid |
JPS62102559A (ja) * | 1985-10-29 | 1987-05-13 | Mitsubishi Electric Corp | 半導体装置及び製造方法 |
US4818723A (en) * | 1985-11-27 | 1989-04-04 | Advanced Micro Devices, Inc. | Silicide contact plug formation technique |
US4666737A (en) * | 1986-02-11 | 1987-05-19 | Harris Corporation | Via metallization using metal fillets |
JPH01501985A (ja) * | 1986-07-31 | 1989-07-06 | アメリカン テレフォン アンド テレグラフ カムパニー | 改良メタライゼーションを有する半導体デバイス |
US4920070A (en) * | 1987-02-19 | 1990-04-24 | Fujitsu Limited | Method for forming wirings for a semiconductor device by filling very narrow via holes |
US4884123A (en) * | 1987-02-19 | 1989-11-28 | Advanced Micro Devices, Inc. | Contact plug and interconnect employing a barrier lining and a backfilled conductor material |
FR2630588A1 (fr) * | 1988-04-22 | 1989-10-27 | Philips Nv | Procede pour realiser une configuration d'interconnexion sur un dispositif semiconducteur notamment un circuit a densite d'integration elevee |
GB8907898D0 (en) | 1989-04-07 | 1989-05-24 | Inmos Ltd | Semiconductor devices and fabrication thereof |
US5188987A (en) * | 1989-04-10 | 1993-02-23 | Kabushiki Kaisha Toshiba | Method of manufacturing a semiconductor device using a polishing step prior to a selective vapor growth step |
JP2726488B2 (ja) * | 1989-04-10 | 1998-03-11 | 株式会社東芝 | 半導体装置の製造方法 |
US5108951A (en) * | 1990-11-05 | 1992-04-28 | Sgs-Thomson Microelectronics, Inc. | Method for forming a metal contact |
US6271137B1 (en) | 1989-11-30 | 2001-08-07 | Stmicroelectronics, Inc. | Method of producing an aluminum stacked contact/via for multilayer |
US5472912A (en) * | 1989-11-30 | 1995-12-05 | Sgs-Thomson Microelectronics, Inc. | Method of making an integrated circuit structure by using a non-conductive plug |
US5658828A (en) * | 1989-11-30 | 1997-08-19 | Sgs-Thomson Microelectronics, Inc. | Method for forming an aluminum contact through an insulating layer |
US6242811B1 (en) | 1989-11-30 | 2001-06-05 | Stmicroelectronics, Inc. | Interlevel contact including aluminum-refractory metal alloy formed during aluminum deposition at an elevated temperature |
US5701027A (en) * | 1991-04-26 | 1997-12-23 | Quicklogic Corporation | Programmable interconnect structures and programmable integrated circuits |
JPH0529475A (ja) * | 1991-07-25 | 1993-02-05 | Mitsubishi Electric Corp | 半導体装置,およびその製造方法 |
US5627345A (en) * | 1991-10-24 | 1997-05-06 | Kawasaki Steel Corporation | Multilevel interconnect structure |
IT1252056B (it) | 1991-11-22 | 1995-05-29 | St Microelectronics Srl | Procedimento per la realizzazione di contatti metallici ad alta stabilita' in un circuito integrato ad uno o piu' livelli di metallizzazione |
US5654568A (en) * | 1992-01-17 | 1997-08-05 | Rohm Co., Ltd. | Semiconductor device including nonvolatile memories |
EP0594300B1 (de) * | 1992-09-22 | 1998-07-29 | STMicroelectronics, Inc. | Methode zur Herstellung eines Metallkontaktes |
EP0720227B1 (de) | 1994-12-29 | 2004-12-01 | STMicroelectronics, Inc. | Elektrische Verbindungsstruktur auf einer integrierten Schaltungsanordnung mit einem Zapfen mit vergrössertem Kopf |
DE69527344T2 (de) * | 1994-12-29 | 2003-02-27 | St Microelectronics Inc | Verfahren zur Herstellung einer Halbleiterverbindungsstruktur |
US5591673A (en) * | 1995-07-05 | 1997-01-07 | Taiwan Semiconductor Manufacturing Company Ltd. | Tungsten stud process for stacked via applications |
US5747383A (en) * | 1995-09-05 | 1998-05-05 | Taiwan Semiconductor Manufacturing Company Ltd | Method for forming conductive lines and stacked vias |
US5661085A (en) * | 1996-06-17 | 1997-08-26 | Chartered Semiconductor Manufacturing Pte, Ltd. | Method for forming a low contact leakage and low contact resistance integrated circuit device electrode |
US5668036A (en) * | 1996-06-21 | 1997-09-16 | Vanguard International Semiconductor Corporation | Fabrication method of the post structure of the cell for high density DRAM |
US6334249B2 (en) | 1997-04-22 | 2002-01-01 | Texas Instruments Incorporated | Cavity-filling method for reducing surface topography and roughness |
US6274486B1 (en) | 1998-09-02 | 2001-08-14 | Micron Technology, Inc. | Metal contact and process |
US6225652B1 (en) * | 1999-08-02 | 2001-05-01 | Clear Logic, Inc. | Vertical laser fuse structure allowing increased packing density |
US6902867B2 (en) * | 2002-10-02 | 2005-06-07 | Lexmark International, Inc. | Ink jet printheads and methods therefor |
US6812056B2 (en) * | 2003-03-05 | 2004-11-02 | Jbcr Innovations, Inc. | Technique for fabricating MEMS devices having diaphragms of “floating” regions of single crystal material |
US7094621B2 (en) * | 2003-03-05 | 2006-08-22 | Jbcr Innovations, L.L.P. | Fabrication of diaphragms and “floating” regions of single crystal semiconductor for MEMS devices |
US6790745B1 (en) | 2003-12-15 | 2004-09-14 | Jbcr Innovations | Fabrication of dielectrically isolated regions of silicon in a substrate |
EP1670066A1 (de) * | 2004-12-08 | 2006-06-14 | St Microelectronics S.A. | Herstellungsverfahren für eine integrierte Schaltung mit eingebettetem Spiegel und entsprechende Schaltung |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5669843A (en) * | 1979-11-09 | 1981-06-11 | Fujitsu Ltd | Manufacture of semiconductor device |
JPS56130920A (en) * | 1980-03-18 | 1981-10-14 | Sharp Corp | Forming method of electrode for semiconductor device |
JPS583250A (ja) * | 1981-06-30 | 1983-01-10 | Toshiba Corp | 半導体装置の製造方法 |
JPS584924A (ja) * | 1981-07-01 | 1983-01-12 | Hitachi Ltd | 半導体装置の電極形成方法 |
JPS5815250A (ja) * | 1981-07-21 | 1983-01-28 | Fujitsu Ltd | 半導体装置の製造方法 |
US4392298A (en) * | 1981-07-27 | 1983-07-12 | Bell Telephone Laboratories, Incorporated | Integrated circuit device connection process |
JPS58162051A (ja) * | 1982-03-23 | 1983-09-26 | Fujitsu Ltd | 半導体装置およびその製造方法 |
JPS5982746A (ja) * | 1982-11-04 | 1984-05-12 | Toshiba Corp | 半導体装置の電極配線方法 |
JPS59154040A (ja) * | 1983-02-22 | 1984-09-03 | Toshiba Corp | 半導体装置の製造方法 |
FR2542920B1 (fr) * | 1983-03-18 | 1986-06-06 | Commissariat Energie Atomique | Procede de positionnement d'une ligne d'interconnexion sur un trou de contact electrique d'un circuit integre |
-
1984
- 1984-04-13 FR FR8405906A patent/FR2563048B1/fr not_active Expired
-
1985
- 1985-04-09 EP EP85400706A patent/EP0165085B1/de not_active Expired
- 1985-04-09 DE DE8585400706T patent/DE3572257D1/de not_active Expired
- 1985-04-10 JP JP60076325A patent/JPS60253245A/ja active Pending
- 1985-04-10 US US06/721,779 patent/US4592802A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
EP0165085A1 (de) | 1985-12-18 |
FR2563048A1 (fr) | 1985-10-18 |
EP0165085B1 (de) | 1989-08-09 |
JPS60253245A (ja) | 1985-12-13 |
US4592802A (en) | 1986-06-03 |
FR2563048B1 (fr) | 1986-05-30 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition |