DE3568515D1 - Method for making studs for interconnecting metallization layers at different levels in semiconductor chip - Google Patents

Method for making studs for interconnecting metallization layers at different levels in semiconductor chip

Info

Publication number
DE3568515D1
DE3568515D1 DE8585110392T DE3568515T DE3568515D1 DE 3568515 D1 DE3568515 D1 DE 3568515D1 DE 8585110392 T DE8585110392 T DE 8585110392T DE 3568515 T DE3568515 T DE 3568515T DE 3568515 D1 DE3568515 D1 DE 3568515D1
Authority
DE
Germany
Prior art keywords
semiconductor chip
different levels
metallization layers
interconnecting metallization
studs
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE8585110392T
Other languages
German (de)
English (en)
Inventor
Thomas Adam Bartush
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE3568515D1 publication Critical patent/DE3568515D1/de
Expired legal-status Critical Current

Links

Classifications

    • H10P95/064—
    • H10W20/063—
    • H10W20/092—
    • H10W20/42—
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/10—Lift-off masking
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/131—Reactive ion etching rie
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y10S438/948—Radiation resist
    • Y10S438/951—Lift-off
DE8585110392T 1984-10-29 1985-08-20 Method for making studs for interconnecting metallization layers at different levels in semiconductor chip Expired DE3568515D1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/665,859 US4541169A (en) 1984-10-29 1984-10-29 Method for making studs for interconnecting metallization layers at different levels in a semiconductor chip

Publications (1)

Publication Number Publication Date
DE3568515D1 true DE3568515D1 (en) 1989-04-06

Family

ID=24671850

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8585110392T Expired DE3568515D1 (en) 1984-10-29 1985-08-20 Method for making studs for interconnecting metallization layers at different levels in semiconductor chip

Country Status (4)

Country Link
US (1) US4541169A (show.php)
EP (1) EP0182977B1 (show.php)
JP (1) JPS61107748A (show.php)
DE (1) DE3568515D1 (show.php)

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US4614021A (en) * 1985-03-29 1986-09-30 Motorola, Inc. Pillar via process
US4742014A (en) * 1985-05-10 1988-05-03 Texas Instruments Incorporated Method of making metal contacts and interconnections for VLSI devices with copper as a primary conductor
US4681795A (en) * 1985-06-24 1987-07-21 The United States Of America As Represented By The Department Of Energy Planarization of metal films for multilevel interconnects
US4674176A (en) * 1985-06-24 1987-06-23 The United States Of America As Represented By The United States Department Of Energy Planarization of metal films for multilevel interconnects by pulsed laser heating
US4954423A (en) * 1985-08-06 1990-09-04 Texas Instruments Incorporated Planar metal interconnection for a VLSI device
US4665007A (en) * 1985-08-19 1987-05-12 International Business Machines Corporation Planarization process for organic filling of deep trenches
US4929992A (en) * 1985-09-18 1990-05-29 Advanced Micro Devices, Inc. MOS transistor construction with self aligned silicided contacts to gate, source, and drain regions
US4922318A (en) * 1985-09-18 1990-05-01 Advanced Micro Devices, Inc. Bipolar and MOS devices fabricated on same integrated circuit substrate
FR2588418B1 (fr) * 1985-10-03 1988-07-29 Bull Sa Procede de formation d'un reseau metallique multicouche d'interconnexion des composants d'un circuit integre de haute densite et circuit integre en resultant
FR2588417B1 (fr) * 1985-10-03 1988-07-29 Bull Sa Procede de formation d'un reseau metallique multicouche d'interconnexion des composants d'un circuit integre de haute densite et circuit integre en resultant
US4642162A (en) * 1986-01-02 1987-02-10 Honeywell Inc. Planarization of dielectric layers in integrated circuits
US4721689A (en) * 1986-08-28 1988-01-26 International Business Machines Corporation Method for simultaneously forming an interconnection level and via studs
US4816112A (en) * 1986-10-27 1989-03-28 International Business Machines Corporation Planarization process through silylation
US4867838A (en) * 1986-10-27 1989-09-19 International Business Machines Corporation Planarization through silylation
US4966865A (en) * 1987-02-05 1990-10-30 Texas Instruments Incorporated Method for planarization of a semiconductor device prior to metallization
US4795722A (en) * 1987-02-05 1989-01-03 Texas Instruments Incorporated Method for planarization of a semiconductor device prior to metallization
NL8701032A (nl) * 1987-05-01 1988-12-01 Philips Nv Werkwijze voor het vervaardigen van een halfgeleiderinrichting met interconnecties die zowel boven een halfgeleidergebied als boven een daaraan grenzend isolatiegebied liggen.
NL8701717A (nl) * 1987-07-21 1989-02-16 Philips Nv Werkwijze voor het vervaardigen van een halfgeleiderinrichting met een geplanariseerde opbouw.
US4879257A (en) * 1987-11-18 1989-11-07 Lsi Logic Corporation Planarization process
US4982266A (en) * 1987-12-23 1991-01-01 Texas Instruments Incorporated Integrated circuit with metal interconnecting layers above and below active circuitry
FR2640427A1 (fr) * 1988-12-09 1990-06-15 Labo Electronique Physique Procede de realisation d'un circuit integre incluant des etapes pour realiser de maniere selective des ouvertures en surface de motifs realises a un dit premier niveau
US5006485A (en) * 1988-12-09 1991-04-09 U.S. Philips Corporation Method of manufacturing an intergrated circuit including steps for forming interconnections between patterns formed at different levels
FR2652201A1 (fr) * 1989-09-19 1991-03-22 Philips Electronique Lab Procede de realisation d'un circuit integre incluant des etapes pour realiser des interconnexions entre des motifs realises a des niveaux differents.
EP0478871B1 (en) * 1990-10-01 2004-04-28 SGS-THOMSON MICROELECTRONICS S.r.l. Formation of contact plugs by blanket CVD deposition and etchback
EP0482247A1 (en) * 1990-10-26 1992-04-29 International Business Machines Corporation Method for producing an integrated circuit structure with a dense multilayer metallization pattern
JPH04348035A (ja) * 1991-05-24 1992-12-03 Nippon Steel Corp 配線形成方法
US5849632A (en) * 1991-08-30 1998-12-15 Micron Technology, Inc. Method of passivating semiconductor wafers
US5320864A (en) * 1992-06-29 1994-06-14 Lsi Logic Corporation Sedimentary deposition of photoresist on semiconductor wafers
US5330883A (en) * 1992-06-29 1994-07-19 Lsi Logic Corporation Techniques for uniformizing photoresist thickness and critical dimension of underlying features
US5856707A (en) * 1995-09-11 1999-01-05 Stmicroelectronics, Inc. Vias and contact plugs with an aspect ratio lower than the aspect ratio of the structure in which they are formed
US6410922B1 (en) 1995-11-29 2002-06-25 Konstantinos Evangelos Spartiotis Forming contacts on semiconductor substrates for radiation detectors and imaging devices
GB2352084B (en) * 1999-07-13 2002-11-13 Simage Oy Forming contacts on semiconductor substrates for radiation detectors and imaging devices
KR100214467B1 (ko) * 1995-12-29 1999-08-02 구본준 반도체소자의 배선구조 형성방법
US6037244A (en) * 1997-03-19 2000-03-14 Advanced Microdevices, Inc. Method of manufacturing a semiconductor device using advanced contact formation
US6162722A (en) * 1999-05-17 2000-12-19 United Microelectronics Corp. Unlanded via process
US7118960B2 (en) * 2000-08-31 2006-10-10 Micron Technology, Inc. Selective polysilicon stud growth
US6380576B1 (en) 2000-08-31 2002-04-30 Micron Technology, Inc. Selective polysilicon stud growth
US6787926B2 (en) * 2001-09-05 2004-09-07 Taiwan Semiconductor Manufacturing Co., Ltd Wire stitch bond on an integrated circuit bond pad and method of making the same
US6787897B2 (en) * 2001-12-20 2004-09-07 Agilent Technologies, Inc. Wafer-level package with silicon gasket
US7294545B2 (en) * 2003-07-02 2007-11-13 Micron Technology, Inc. Selective polysilicon stud growth
US20060278912A1 (en) * 2004-09-02 2006-12-14 Luan Tran Selective polysilicon stud growth
US10879108B2 (en) * 2016-11-15 2020-12-29 Taiwan Semiconductor Manufacturing Co., Ltd. Topographic planarization method for lithography process

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4835778A (show.php) * 1971-09-09 1973-05-26
US3976524A (en) * 1974-06-17 1976-08-24 Ibm Corporation Planarization of integrated circuit surfaces through selective photoresist masking
DE2547792C3 (de) * 1974-10-25 1978-08-31 Hitachi, Ltd., Tokio Verfahren zur Herstellung eines Halbleiterbauelementes
US4007103A (en) * 1975-10-14 1977-02-08 Ibm Corporation Planarizing insulative layers by resputtering
DE2629996A1 (de) * 1976-07-03 1978-01-05 Ibm Deutschland Verfahren zur passivierung und planarisierung eines metallisierungsmusters
US4410622A (en) * 1978-12-29 1983-10-18 International Business Machines Corporation Forming interconnections for multilevel interconnection metallurgy systems
US4333227A (en) * 1979-11-29 1982-06-08 International Business Machines Corporation Process for fabricating a self-aligned micrometer bipolar transistor device
US4367119A (en) * 1980-08-18 1983-01-04 International Business Machines Corporation Planar multi-level metal process with built-in etch stop
US4307180A (en) * 1980-08-22 1981-12-22 International Business Machines Corp. Process of forming recessed dielectric regions in a monocrystalline silicon substrate
JPS5848936A (ja) * 1981-09-10 1983-03-23 Fujitsu Ltd 半導体装置の製造方法
US4470874A (en) * 1983-12-15 1984-09-11 International Business Machines Corporation Planarization of multi-level interconnected metallization system

Also Published As

Publication number Publication date
JPH033383B2 (show.php) 1991-01-18
EP0182977A1 (en) 1986-06-04
US4541169A (en) 1985-09-17
JPS61107748A (ja) 1986-05-26
EP0182977B1 (en) 1989-03-01

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee