DE3545433C2 - - Google Patents

Info

Publication number
DE3545433C2
DE3545433C2 DE19853545433 DE3545433A DE3545433C2 DE 3545433 C2 DE3545433 C2 DE 3545433C2 DE 19853545433 DE19853545433 DE 19853545433 DE 3545433 A DE3545433 A DE 3545433A DE 3545433 C2 DE3545433 C2 DE 3545433C2
Authority
DE
Germany
Prior art keywords
adder
output
stage
basic
basic cells
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE19853545433
Other languages
German (de)
English (en)
Other versions
DE3545433A1 (de
Inventor
Makoto Yokohama Jp Noda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Publication of DE3545433A1 publication Critical patent/DE3545433A1/de
Application granted granted Critical
Publication of DE3545433C2 publication Critical patent/DE3545433C2/de
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • G06F7/53—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel
    • G06F7/5306—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel with row wise addition of partial products
    • G06F7/5312—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel with row wise addition of partial products using carry save adders

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Complex Calculations (AREA)
DE19853545433 1984-12-28 1985-12-20 Parallelmultiplizierschaltung Granted DE3545433A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59276259A JPS61156433A (ja) 1984-12-28 1984-12-28 並列乗算器

Publications (2)

Publication Number Publication Date
DE3545433A1 DE3545433A1 (de) 1986-07-03
DE3545433C2 true DE3545433C2 (enrdf_load_stackoverflow) 1992-10-01

Family

ID=17566932

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19853545433 Granted DE3545433A1 (de) 1984-12-28 1985-12-20 Parallelmultiplizierschaltung

Country Status (2)

Country Link
JP (1) JPS61156433A (enrdf_load_stackoverflow)
DE (1) DE3545433A1 (enrdf_load_stackoverflow)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4864529A (en) * 1986-10-09 1989-09-05 North American Philips Corporation Fast multiplier architecture
US4958312A (en) * 1987-11-09 1990-09-18 Lsi Logic Corporation Digital multiplier circuit and a digital multiplier-accumulator circuit which preloads and accumulates subresults
US5734601A (en) * 1995-01-30 1998-03-31 Cirrus Logic, Inc. Booth multiplier with low power, high performance input circuitry
US5638313A (en) * 1995-01-30 1997-06-10 Cirrus Logic, Inc. Booth multiplier with high speed output circuitry
DE19528210C1 (de) * 1995-08-01 1996-12-19 Siemens Ag Halbleiter-Baustein mit mindestens einer Schaltungsanordnung zur eingeschränkten Bearbeitung von an Eingangsanschlüssen des Bausteins anliegenden Eingangsgrößen
US7401110B1 (en) * 2004-09-09 2008-07-15 Sun Microsystems, Inc. System, method and apparatus for an improved MD5 hash algorithm

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4168530A (en) * 1978-02-13 1979-09-18 Burroughs Corporation Multiplication circuit using column compression
US4130878A (en) * 1978-04-03 1978-12-19 Motorola, Inc. Expandable 4 × 8 array multiplier
JPS55105732A (en) * 1979-02-08 1980-08-13 Nippon Telegr & Teleph Corp <Ntt> Multiplier
JPS57141753A (en) * 1981-02-25 1982-09-02 Nec Corp Multiplication circuit

Also Published As

Publication number Publication date
JPS61156433A (ja) 1986-07-16
JPH0418336B2 (enrdf_load_stackoverflow) 1992-03-27
DE3545433A1 (de) 1986-07-03

Similar Documents

Publication Publication Date Title
DE3700991C2 (de) Digitaler Übertragsvorgriffsaddierer
DE2523860C3 (de) Vorrichtung zur digitalen, linearen Interpolation einer fabulierten Funktion
DE19758079A1 (de) Verfahren und Vorrichtung zur Galoisfeld-Multiplikation
DE2803425A1 (de) Digitaleinrichtung zur ermittlung des wertes von komplexen arithmetischen ausdruecken
DE4101004C2 (de) Paralleler Multiplizierer mit Sprungfeld und modifiziertem Wallac-Baum
DE69506045T2 (de) Logikschaltung zur parallelen Multiplikation
DE4409834C2 (de) Multiplizierschaltung
DE3545433C2 (enrdf_load_stackoverflow)
EP0139207B1 (de) Schaltung zur CSD-Codierung einer im Zweierkomplement dargestellten, binären Zahl
EP0130397B1 (de) Digitales Rechenwerk
DE2750212A1 (de) Einrichtung zur bildung und akkumulation von produkten
DE3447634C2 (enrdf_load_stackoverflow)
DE2727051C3 (de) Einrichtung zur binären Multiplikation einer ersten Zahl als Multiplikand mit einer den Multiplikator ergebenden Summe aus einer zweiten und dritten Zahl im Binärcode
DE2705989C2 (de) Schaltungsanordnung zum parallelen Addieren oder Subtrahieren von mindestens zwei Eingangszahlen
DE3326388C2 (enrdf_load_stackoverflow)
DE3046772C2 (de) Taktgenerator
DE2017132A1 (de) Binarer Parallel Addierer
DE19644688A1 (de) Schaltungsanordnung einer digitalen Multiplizierer-Baugruppe, zur Verarbeitung von Binärzahlen sowie Elementen aus GF(2 APPROX )
DE69231911T2 (de) Digitale Multipliziererschaltung
EP0333884B1 (de) CMOS-Parallel-Serien-Multiplizierschaltung sowie deren Multiplizier- und Addierstufen
EP0752130B1 (de) Multiplizierer mit geringer laufzeit
DE1524156A1 (de) Elektronische Recheneinrichtung
EP0416153B1 (de) Verfahren für Datenverarbeitungsanlagen zur Division von, zu Beginn jeweils normalisierten, beliebig langen Operanden und Divisionswerk zur Durchführung des Verfahrens
DE3823722A1 (de) Multiplizierer
DE1524177C (de) Multiplikationseinrichtung zur teilweise parallelen Multiplikation binärer Faktoren

Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
D2 Grant after examination
8364 No opposition during term of opposition
8320 Willingness to grant licenses declared (paragraph 23)