DE69231911T2 - Digitale Multipliziererschaltung - Google Patents

Digitale Multipliziererschaltung

Info

Publication number
DE69231911T2
DE69231911T2 DE1992631911 DE69231911T DE69231911T2 DE 69231911 T2 DE69231911 T2 DE 69231911T2 DE 1992631911 DE1992631911 DE 1992631911 DE 69231911 T DE69231911 T DE 69231911T DE 69231911 T2 DE69231911 T2 DE 69231911T2
Authority
DE
Germany
Prior art keywords
multiplier circuit
digital multiplier
digital
circuit
multiplier
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE1992631911
Other languages
English (en)
Other versions
DE69231911D1 (de
Inventor
Takao Yamazaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Publication of DE69231911D1 publication Critical patent/DE69231911D1/de
Application granted granted Critical
Publication of DE69231911T2 publication Critical patent/DE69231911T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • G06F7/533—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even
    • G06F7/5334—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product
    • G06F7/5336—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product overlapped, i.e. with successive bitgroups sharing one or more bits being recoded into signed digit representation, e.g. using the Modified Booth Algorithm
    • G06F7/5338—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product overlapped, i.e. with successive bitgroups sharing one or more bits being recoded into signed digit representation, e.g. using the Modified Booth Algorithm each bitgroup having two new bits, e.g. 2nd order MBA
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/3804—Details
    • G06F2207/386—Special constructional features
    • G06F2207/3884—Pipelining
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/499—Denomination or exception handling, e.g. rounding or overflow
    • G06F7/49942—Significance control
    • G06F7/49947—Rounding
    • G06F7/49963—Rounding to nearest
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/499—Denomination or exception handling, e.g. rounding or overflow
    • G06F7/49994—Sign extension

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Complex Calculations (AREA)
DE1992631911 1991-11-29 1992-11-30 Digitale Multipliziererschaltung Expired - Fee Related DE69231911T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3342168A JPH05150950A (ja) 1991-11-29 1991-11-29 乗算回路

Publications (2)

Publication Number Publication Date
DE69231911D1 DE69231911D1 (de) 2001-08-09
DE69231911T2 true DE69231911T2 (de) 2002-04-04

Family

ID=18351651

Family Applications (1)

Application Number Title Priority Date Filing Date
DE1992631911 Expired - Fee Related DE69231911T2 (de) 1991-11-29 1992-11-30 Digitale Multipliziererschaltung

Country Status (3)

Country Link
EP (1) EP0545654B1 (de)
JP (1) JPH05150950A (de)
DE (1) DE69231911T2 (de)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2722590B1 (fr) * 1994-07-15 1996-09-06 Sgs Thomson Microelectronics Circuit logique de multiplication parallele
KR0158647B1 (ko) * 1995-05-22 1998-12-15 윤종용 부호/무부호 수 겸용 곱셈기
JP3678512B2 (ja) 1996-08-29 2005-08-03 富士通株式会社 乗算回路、該乗算回路を構成する加算回路、該乗算回路の部分積ビット圧縮方法、および、該乗算回路を適用した大規模半導体集積回路
JPH10133856A (ja) * 1996-10-31 1998-05-22 Nec Corp 丸め機能付き乗算方法及び乗算器

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2526287B2 (ja) * 1989-05-30 1996-08-21 富士通株式会社 演算回路
DE69032391T2 (de) * 1989-11-13 1998-10-29 Harris Corp Mehrere Bit umkodierender Multiplizierer

Also Published As

Publication number Publication date
DE69231911D1 (de) 2001-08-09
JPH05150950A (ja) 1993-06-18
EP0545654A2 (de) 1993-06-09
EP0545654A3 (en) 1993-10-27
EP0545654B1 (de) 2001-07-04

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee