DE3485051D1 - Paralleladdierschaltung. - Google Patents

Paralleladdierschaltung.

Info

Publication number
DE3485051D1
DE3485051D1 DE8484114286T DE3485051T DE3485051D1 DE 3485051 D1 DE3485051 D1 DE 3485051D1 DE 8484114286 T DE8484114286 T DE 8484114286T DE 3485051 T DE3485051 T DE 3485051T DE 3485051 D1 DE3485051 D1 DE 3485051D1
Authority
DE
Germany
Prior art keywords
parallel charger
charger
parallel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE8484114286T
Other languages
English (en)
Inventor
Masayuki C O Patent Div Sahoda
Fuminari C O Patent Div Tanaka
Tetsuya C O Patent Divisi Iida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of DE3485051D1 publication Critical patent/DE3485051D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/501—Half or full adders, i.e. basic adder cells for one denomination
    • G06F7/502—Half adders; Full adders consisting of two cascaded half adders
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/3804—Details
    • G06F2207/386—Special constructional features
    • G06F2207/3876—Alternation of true and inverted stages

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)
  • Logic Circuits (AREA)
DE8484114286T 1983-11-28 1984-11-26 Paralleladdierschaltung. Expired - Lifetime DE3485051D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58223553A JPS60116034A (ja) 1983-11-28 1983-11-28 加算回路

Publications (1)

Publication Number Publication Date
DE3485051D1 true DE3485051D1 (de) 1991-10-17

Family

ID=16799958

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8484114286T Expired - Lifetime DE3485051D1 (de) 1983-11-28 1984-11-26 Paralleladdierschaltung.

Country Status (4)

Country Link
US (1) US4701877A (de)
EP (1) EP0143456B1 (de)
JP (1) JPS60116034A (de)
DE (1) DE3485051D1 (de)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6232532A (ja) * 1985-08-05 1987-02-12 Mitsubishi Electric Corp 論理回路
EP0224656B1 (de) * 1985-09-30 1992-12-30 Siemens Aktiengesellschaft Mehrstelliger Carry-Ripple-Addierer in CMOS-Technik mit zwei Typen von Addiererzellen
US4783757A (en) * 1985-12-24 1988-11-08 Intel Corporation Three input binary adder
EP0238678B1 (de) * 1986-03-22 1990-09-19 Deutsche ITT Industries GmbH CMOS-Volladdierstufe
JPH063578B2 (ja) * 1986-12-24 1994-01-12 松下電器産業株式会社 演算処理装置
US5031136A (en) * 1986-06-27 1991-07-09 Matsushita Electric Industrial Co., Ltd. Signed-digit arithmetic processing units with binary operands
JPS6382515A (ja) * 1986-09-27 1988-04-13 Toshiba Corp 加算器
FR2612660B1 (fr) * 1987-03-18 1990-10-19 Hmida Hedi Dispositif de calcul binaire
JP2607538B2 (ja) * 1987-08-28 1997-05-07 株式会社日立製作所 加算回路
EP0309348B1 (de) * 1987-09-23 1993-04-21 France Telecom Binäre Additions- und Multiplikationsvorrichtung
US5047975A (en) * 1987-11-16 1991-09-10 Intel Corporation Dual mode adder circuitry with overflow detection and substitution enabled for a particular mode
JPH0224045U (de) * 1988-08-03 1990-02-16
KR960004572B1 (ko) * 1994-01-28 1996-04-09 금성일렉트론주식회사 산술연산 논리회로
FR2716759B1 (fr) * 1994-02-28 1996-04-05 Sgs Thomson Microelectronics Etage de formatage d'opérandes optimisé.
US5633820A (en) * 1995-06-05 1997-05-27 International Business Machines Corporation Self-resetting CMOS parallel adder with a bubble pipelined architecture, tri-rail merging logic, and enhanced testability

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3100837A (en) * 1960-08-22 1963-08-13 Rca Corp Adder-subtracter
US4052604A (en) * 1976-01-19 1977-10-04 Hewlett-Packard Company Binary adder
JPS56147235A (en) * 1980-04-17 1981-11-16 Toshiba Corp Carry signal generating circuit
FR2516675A1 (fr) * 1981-11-19 1983-05-20 Labo Cent Telecommunicat Cellule d'addition binaire a trois entrees a propagation rapide de la retenue
JPS58213342A (ja) * 1982-06-04 1983-12-12 Matsushita Electric Ind Co Ltd 加算回路
US4523292A (en) * 1982-09-30 1985-06-11 Rca Corporation Complementary FET ripple carry binary adder circuit
JPS59139447A (ja) * 1983-01-28 1984-08-10 Matsushita Electric Ind Co Ltd 全加算器

Also Published As

Publication number Publication date
EP0143456B1 (de) 1991-09-11
EP0143456A2 (de) 1985-06-05
US4701877A (en) 1987-10-20
JPS60116034A (ja) 1985-06-22
EP0143456A3 (en) 1988-05-18

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee