DE3484519D1 - Halbleiterspeicheranordnung. - Google Patents

Halbleiterspeicheranordnung.

Info

Publication number
DE3484519D1
DE3484519D1 DE8484300789T DE3484519T DE3484519D1 DE 3484519 D1 DE3484519 D1 DE 3484519D1 DE 8484300789 T DE8484300789 T DE 8484300789T DE 3484519 T DE3484519 T DE 3484519T DE 3484519 D1 DE3484519 D1 DE 3484519D1
Authority
DE
Germany
Prior art keywords
semiconductor memory
memory arrangement
arrangement
semiconductor
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8484300789T
Other languages
English (en)
Inventor
Masanobu Yoshida
Kiyoshi Itano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of DE3484519D1 publication Critical patent/DE3484519D1/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Memories (AREA)
  • Static Random-Access Memory (AREA)
DE8484300789T 1983-02-10 1984-02-08 Halbleiterspeicheranordnung. Expired - Fee Related DE3484519D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58019697A JPS59161061A (ja) 1983-02-10 1983-02-10 半導体記憶装置

Publications (1)

Publication Number Publication Date
DE3484519D1 true DE3484519D1 (de) 1991-06-06

Family

ID=12006450

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8484300789T Expired - Fee Related DE3484519D1 (de) 1983-02-10 1984-02-08 Halbleiterspeicheranordnung.

Country Status (4)

Country Link
US (1) US4615021A (de)
EP (1) EP0119002B1 (de)
JP (1) JPS59161061A (de)
DE (1) DE3484519D1 (de)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61110459A (ja) * 1984-11-02 1986-05-28 Nippon Telegr & Teleph Corp <Ntt> 半導体メモリ
US4695978A (en) * 1984-11-15 1987-09-22 Fujitsu Limited Semiconductor memory device
KR950008676B1 (ko) * 1986-04-23 1995-08-04 가부시기가이샤 히다찌세이사꾸쇼 반도체 메모리 장치 및 그의 결함 구제 방법
US4797858A (en) * 1987-03-30 1989-01-10 Motorola, Inc. Semiconductor memory with divided word lines and shared sense amplifiers
JPH0391193A (ja) * 1989-08-31 1991-04-16 Fujitsu Ltd 半導体記憶装置
JPH06187793A (ja) * 1992-12-18 1994-07-08 Kawasaki Steel Corp 半導体メモリ
JP3129880B2 (ja) * 1993-06-18 2001-01-31 株式会社東芝 半導体記憶装置
US5636158A (en) * 1995-03-13 1997-06-03 Kabushiki Kaisha Toshiba Irregular pitch layout for a semiconductor memory device

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3387286A (en) * 1967-07-14 1968-06-04 Ibm Field-effect transistor memory
US3702466A (en) * 1969-11-05 1972-11-07 Nippon Electric Co Semiconductor integrated circuit memory device utilizing insulated gate type semiconductor elements
IT1135038B (it) * 1980-01-28 1986-08-20 Rca Corp Apparato per unire elettricamente le estremita' di linee di materiale semiconduttore,sostanzialmente parallele
JPS6027119B2 (ja) * 1980-04-22 1985-06-27 株式会社東芝 半導体メモリ
JPS6059677B2 (ja) * 1981-08-19 1985-12-26 富士通株式会社 半導体記憶装置

Also Published As

Publication number Publication date
JPS59161061A (ja) 1984-09-11
EP0119002A3 (en) 1988-01-27
JPS6332271B2 (de) 1988-06-29
EP0119002B1 (de) 1991-05-02
EP0119002A2 (de) 1984-09-19
US4615021A (en) 1986-09-30

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee