DE3483717D1 - Verfahren zur herstellung von halbleiterstrukturen. - Google Patents

Verfahren zur herstellung von halbleiterstrukturen.

Info

Publication number
DE3483717D1
DE3483717D1 DE8484902421T DE3483717T DE3483717D1 DE 3483717 D1 DE3483717 D1 DE 3483717D1 DE 8484902421 T DE8484902421 T DE 8484902421T DE 3483717 T DE3483717 T DE 3483717T DE 3483717 D1 DE3483717 D1 DE 3483717D1
Authority
DE
Germany
Prior art keywords
semiconductor structures
producing semiconductor
producing
structures
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE8484902421T
Other languages
English (en)
Inventor
Paul Sobczak
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NCR International Inc
Original Assignee
NCR Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NCR Corp filed Critical NCR Corp
Application granted granted Critical
Publication of DE3483717D1 publication Critical patent/DE3483717D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H01L21/31055—Planarisation of the insulating layers involving a dielectric removal step the removal being a chemical etching step, e.g. dry etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76281—Lateral isolation by selective oxidation of silicon

Landscapes

  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Inorganic Chemistry (AREA)
  • Element Separation (AREA)
DE8484902421T 1983-06-13 1984-06-07 Verfahren zur herstellung von halbleiterstrukturen. Expired - Lifetime DE3483717D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US50399783A 1983-06-13 1983-06-13
PCT/US1984/000877 WO1984004996A1 (en) 1983-06-13 1984-06-07 Process for fabricating semiconductor structures

Publications (1)

Publication Number Publication Date
DE3483717D1 true DE3483717D1 (de) 1991-01-17

Family

ID=24004435

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8484902421T Expired - Lifetime DE3483717D1 (de) 1983-06-13 1984-06-07 Verfahren zur herstellung von halbleiterstrukturen.

Country Status (4)

Country Link
EP (1) EP0146613B1 (de)
JP (1) JPH0642510B2 (de)
DE (1) DE3483717D1 (de)
WO (1) WO1984004996A1 (de)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0244848A1 (de) * 1986-05-07 1987-11-11 Siemens Aktiengesellschaft Verfahren zum Planarisieren von anorganischen, als Zwischenschichten bei Mehrlagenmetallisierung verwendbaren Isolationsschichten
WO1996016437A1 (en) * 1994-11-18 1996-05-30 Advanced Micro Devices, Inc. Silicon nitride etch process with critical dimension gain
US5444014A (en) * 1994-12-16 1995-08-22 Electronics And Telecommunications Research Institute Method for fabricating semiconductor device
US6841003B2 (en) * 2002-11-22 2005-01-11 Cdream Display Corporation Method for forming carbon nanotubes with intermediate purification steps

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2547792C3 (de) * 1974-10-25 1978-08-31 Hitachi, Ltd., Tokio Verfahren zur Herstellung eines Halbleiterbauelementes
JPS6028387B2 (ja) * 1979-07-12 1985-07-04 松下電器産業株式会社 半導体装置の製造方法
US4307180A (en) * 1980-08-22 1981-12-22 International Business Machines Corp. Process of forming recessed dielectric regions in a monocrystalline silicon substrate
JPS57154856A (en) * 1981-03-19 1982-09-24 Toshiba Corp Semiconductor device
US4407851A (en) * 1981-04-13 1983-10-04 Tokyo Shibaura Denki Kabushiki Kaisha Method for manufacturing semiconductor device
US4361600A (en) * 1981-11-12 1982-11-30 General Electric Company Method of making integrated circuits
US4502913A (en) * 1982-06-30 1985-03-05 International Business Machines Corporation Total dielectric isolation for integrated circuits

Also Published As

Publication number Publication date
EP0146613B1 (de) 1990-12-05
EP0146613A4 (de) 1987-08-24
EP0146613A1 (de) 1985-07-03
JPH0642510B2 (ja) 1994-06-01
JPS60501583A (ja) 1985-09-19
WO1984004996A1 (en) 1984-12-20

Similar Documents

Publication Publication Date Title
DE3485880D1 (de) Verfahren zur herstellung von halbleiteranordnungen.
DE3486147D1 (de) Verfahren zur herstellung von l-isoleucin.
DE3483659D1 (de) Verfahren zur herstellung von polycide-strukturen.
DE3767431D1 (de) Verfahren zur herstellung von halbleiterbauelementen.
DE3587442D1 (de) Verfahren zur herstellung von polysilsesquioxanen.
DE3581200D1 (de) Verfahren zur herstellung von 1-hydroxyvitamin-d-verbindungen.
DE3585687D1 (de) Verfahren zur herstellung von 1-hydroxyvitamin-d-verbindungen.
DE3575423D1 (de) Verfahren zur herstellung von heteroaryloxyacetamiden.
AT383808B (de) Verfahren zur herstellung von penemen
DE3586638D1 (de) Verfahren zur herstellung von vanadylphthalocyanin.
DE3578062D1 (de) Verfahren zur herstellung von iodbenzol.
DE3486006D1 (de) Verfahren zur herstellung von halbleiterlasern.
DE3485089D1 (de) Verfahren zur herstellung von halbleitervorrichtungen.
DE3483974D1 (de) Verfahren zur herstellung von bildern.
DE3481416D1 (de) Verfahren zur herstellung von thiazolyl-2-sulfenamiden.
DE3580626D1 (de) Verfahren zur herstellung von schleifmitteln.
DE3381934D1 (de) Verfahren zur herstellung von shampoos.
DE3584173D1 (de) Verfahren zur herstellung von l-phenylalanin.
DE3483599D1 (de) Verfahren zur herstellung von riboflavin.
DE3771806D1 (de) Verfahren zur herstellung von 3-halogen-2-hydroxypropyl-trimethylammonium-halogenid.
DE3382369D1 (de) Verfahren zur herstellung von blockcopolyamiden.
DE3585219D1 (de) Verfahren zur herstellung von n-formyl-alpha-aspartyl-phenylalaninen.
DE3576817D1 (de) Verfahren zur herstellung von aminen.
DE3575133D1 (de) Verfahren zur herstellung von 1-alkyl- oder 1-cycloalkylpiperazinen.
DE3579858D1 (de) Verfahren zur herstellung von p-isobutylstyrol.

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: NCR INTERNATIONAL INC., DAYTON, OHIO, US

8328 Change in the person/name/address of the agent

Free format text: KAHLER, K., DIPL.-ING., 8948 MINDELHEIM KAECK, J., DIPL.-ING. DIPL.-WIRTSCH.-ING., 8910 LANDSBERG FIENER, J., PAT.-ANWAELTE, 8948 MINDELHEIM

8327 Change in the person/name/address of the patent owner

Owner name: AT&T GLOBAL INFORMATION SOLUTIONS INTERNATIONAL IN

8327 Change in the person/name/address of the patent owner

Owner name: AT&T GLOBAL INFORMATION SOLUTIONS INTERNATIONAL IN

8327 Change in the person/name/address of the patent owner

Owner name: NCR INTERNATIONAL, INC. (N.D.GES.D.STAATES DELAWAR

8327 Change in the person/name/address of the patent owner

Owner name: NCR INTERNATIONAL, INC. (N.D.GES.D.STAATES DELAWAR

8328 Change in the person/name/address of the agent

Free format text: V. BEZOLD & SOZIEN, 80799 MUENCHEN