DE3481148D1 - Verfahren zur herstellung von halbleiteranordnungen mittels einer behandlung mit hoher temperatur in einer oxydierenden atmosphaere. - Google Patents

Verfahren zur herstellung von halbleiteranordnungen mittels einer behandlung mit hoher temperatur in einer oxydierenden atmosphaere.

Info

Publication number
DE3481148D1
DE3481148D1 DE8484114427T DE3481148T DE3481148D1 DE 3481148 D1 DE3481148 D1 DE 3481148D1 DE 8484114427 T DE8484114427 T DE 8484114427T DE 3481148 T DE3481148 T DE 3481148T DE 3481148 D1 DE3481148 D1 DE 3481148D1
Authority
DE
Germany
Prior art keywords
oxyding
atmosphere
high temperature
producing semiconductor
treating high
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE8484114427T
Other languages
German (de)
English (en)
Inventor
Henry John Geipel Jr
Charles Andrew Schaefer
Francis Roger White
John Michael Wursthorn
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE3481148D1 publication Critical patent/DE3481148D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H10P14/6502—
    • H10P14/6308—
    • H10P14/6309—
    • H10P14/6322—
    • H10P14/69215—
    • H10P95/90—
    • H10P14/6927—
    • H10P14/69433—
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/911—Differential oxidation and etching
DE8484114427T 1983-12-23 1984-11-30 Verfahren zur herstellung von halbleiteranordnungen mittels einer behandlung mit hoher temperatur in einer oxydierenden atmosphaere. Expired - Lifetime DE3481148D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/564,880 US4527325A (en) 1983-12-23 1983-12-23 Process for fabricating semiconductor devices utilizing a protective film during high temperature annealing

Publications (1)

Publication Number Publication Date
DE3481148D1 true DE3481148D1 (de) 1990-03-01

Family

ID=24256275

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8484114427T Expired - Lifetime DE3481148D1 (de) 1983-12-23 1984-11-30 Verfahren zur herstellung von halbleiteranordnungen mittels einer behandlung mit hoher temperatur in einer oxydierenden atmosphaere.

Country Status (4)

Country Link
US (1) US4527325A (cg-RX-API-DMAC10.html)
EP (1) EP0158715B1 (cg-RX-API-DMAC10.html)
JP (1) JPS60136319A (cg-RX-API-DMAC10.html)
DE (1) DE3481148D1 (cg-RX-API-DMAC10.html)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0173953B1 (en) * 1984-08-28 1991-07-17 Kabushiki Kaisha Toshiba Method for manufacturing a semiconductor device having a gate electrode
JP2644776B2 (ja) * 1987-11-02 1997-08-25 株式会社日立製作所 半導体装置及びその製造方法
US5252501A (en) * 1991-12-30 1993-10-12 Texas Instruments Incorporated Self-aligned single-mask CMOS/BiCMOS twin-well formation with flat surface topography
US5770492A (en) * 1995-06-07 1998-06-23 Lsi Logic Corporation Self-aligned twin well process
US5763302A (en) * 1995-06-07 1998-06-09 Lsi Logic Corporation Self-aligned twin well process
US5583062A (en) * 1995-06-07 1996-12-10 Lsi Logic Corporation Self-aligned twin well process having a SiO2 -polysilicon-SiO2 barrier mask
US5670393A (en) * 1995-07-12 1997-09-23 Lsi Logic Corporation Method of making combined metal oxide semiconductor and junction field effect transistor device
US5872052A (en) * 1996-02-12 1999-02-16 Micron Technology, Inc. Planarization using plasma oxidized amorphous silicon
US6297170B1 (en) 1998-06-23 2001-10-02 Vlsi Technology, Inc. Sacrificial multilayer anti-reflective coating for mos gate formation
US11791271B2 (en) * 2020-09-30 2023-10-17 Tokyo Electron Limited Monolithic formation of a set of interconnects below active devices

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3921283A (en) * 1971-06-08 1975-11-25 Philips Corp Semiconductor device and method of manufacturing the device
US3999213A (en) * 1972-04-14 1976-12-21 U.S. Philips Corporation Semiconductor device and method of manufacturing the device
US3911168A (en) * 1973-06-01 1975-10-07 Fairchild Camera Instr Co Method for forming a continuous layer of silicon dioxide over a substrate
US3920481A (en) * 1974-06-03 1975-11-18 Fairchild Camera Instr Co Process for fabricating insulated gate field effect transistor structure
GB1559583A (en) * 1975-07-18 1980-01-23 Tokyo Shibaura Electric Co Complementary mosfet device and method of manufacturing the same
US4214917A (en) * 1978-02-10 1980-07-29 Emm Semi Process of forming a semiconductor memory cell with continuous polysilicon run circuit elements
JPS5693344A (en) * 1979-12-26 1981-07-28 Fujitsu Ltd Manufacture of semiconductor device
US4240845A (en) * 1980-02-04 1980-12-23 International Business Machines Corporation Method of fabricating random access memory device
US4398338A (en) * 1980-12-24 1983-08-16 Fairchild Camera & Instrument Corp. Fabrication of high speed, nonvolatile, electrically erasable memory cell and system utilizing selective masking, deposition and etching techniques
US4412375A (en) * 1982-06-10 1983-11-01 Intel Corporation Method for fabricating CMOS devices with guardband
GB2140202A (en) * 1983-05-16 1984-11-21 Philips Electronic Associated Methods of manufacturing semiconductor devices

Also Published As

Publication number Publication date
US4527325A (en) 1985-07-09
JPS60136319A (ja) 1985-07-19
JPH032338B2 (cg-RX-API-DMAC10.html) 1991-01-14
EP0158715A2 (en) 1985-10-23
EP0158715B1 (en) 1990-01-24
EP0158715A3 (en) 1986-07-16

Similar Documents

Publication Publication Date Title
DE3485880D1 (de) Verfahren zur herstellung von halbleiteranordnungen.
DE3767431D1 (de) Verfahren zur herstellung von halbleiterbauelementen.
DE3587617D1 (de) Verfahren zur herstellung von bipolaren halbleiteranordnungen.
DE69104226D1 (de) Vorrichtung und verfahren zur behandlung von salzen mittels elektrodialyse zur herstellung von säuren und/oder basen hoher reinheit.
DE3486006D1 (de) Verfahren zur herstellung von halbleiterlasern.
DE3485089D1 (de) Verfahren zur herstellung von halbleitervorrichtungen.
DE3481148D1 (de) Verfahren zur herstellung von halbleiteranordnungen mittels einer behandlung mit hoher temperatur in einer oxydierenden atmosphaere.
DE3771751D1 (de) Verfahren zur herstellung von polyarylenthioaethern mit hoher stabilitaet.
DE3680190D1 (de) Verfahren zur herstellung von halbleiterlasern.
DE3485160D1 (de) Verfahren zum aetzen verwendet bei der herstellung von halbleiteranordnungen.
DE3783418D1 (de) Verfahren zur herstellung einer halbleiterschaltung mit hoher durchbruchspannung.
DE3667271D1 (de) Verfahren zur herstellung von 5-ethyliden-2-norbornen von hoher qualitaet.
AT373613B (de) Verfahren zur herstellung von polysiloxanen
AT380463B (de) Verfahren zur herstellung von silizium
AT348545B (de) Verfahren zur herstellung von 1-aminoalkan-1,1- diphosphonsaeuren
AT363978B (de) Verfahren zur herstellung von elektromagnetischen, kornorientierten siliciumstaehlen
DE3585633D1 (de) Verfahren und vorrichtung zur herstellung von kalziniertem koks hoher qualitaet.
AT379161B (de) Verfahren zur herstellung von elastomer-duromer-verbundteilen
AT364813B (de) Verfahren zur herstellung von alpha-aryl-alpha, alpha-di(omega-aminoalkyl)acetamiden mit disubstituierter aminogruppe
AT364345B (de) Verfahren zur herstellung von n-aethylaethylendiamin
DE69027836D1 (de) Verfahren zur herstellung von halbleiteranordnungen
DD128421A5 (de) Verfahren zur herstellung von halogenacetalen aus enoxysilanen
DE3483717D1 (de) Verfahren zur herstellung von halbleiterstrukturen.
DD134469A5 (de) Verfahren zur herstellung von elektrischen widerstaenden
AT362009B (de) Verfahren zur herstellung von leiterplatten

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee