DE3469067D1 - Method and circuit for oscillation prevention during testing of integrated circuit logic chips - Google Patents

Method and circuit for oscillation prevention during testing of integrated circuit logic chips

Info

Publication number
DE3469067D1
DE3469067D1 DE8484111867T DE3469067T DE3469067D1 DE 3469067 D1 DE3469067 D1 DE 3469067D1 DE 8484111867 T DE8484111867 T DE 8484111867T DE 3469067 T DE3469067 T DE 3469067T DE 3469067 D1 DE3469067 D1 DE 3469067D1
Authority
DE
Germany
Prior art keywords
chip
inhibit
driver
receiver
logic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE8484111867T
Other languages
German (de)
English (en)
Inventor
Charles Wei-Yuan Cha
John William Hartman
David Alan Kiesling
William Scarpero
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE3469067D1 publication Critical patent/DE3469067D1/de
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31917—Stimuli generation or application of test patterns to the device under test [DUT]
    • G01R31/31924—Voltage or current aspects, e.g. driver, receiver
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31903—Tester hardware, i.e. output processing circuits tester configuration
    • G01R31/31905—Interface with the device under test [DUT], e.g. arrangements between the test head and the DUT, mechanical aspects, fixture

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
DE8484111867T 1983-10-07 1984-10-04 Method and circuit for oscillation prevention during testing of integrated circuit logic chips Expired DE3469067D1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/540,072 US4553049A (en) 1983-10-07 1983-10-07 Oscillation prevention during testing of integrated circuit logic chips

Publications (1)

Publication Number Publication Date
DE3469067D1 true DE3469067D1 (en) 1988-03-03

Family

ID=24153869

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8484111867T Expired DE3469067D1 (en) 1983-10-07 1984-10-04 Method and circuit for oscillation prevention during testing of integrated circuit logic chips

Country Status (4)

Country Link
US (1) US4553049A (https=)
EP (1) EP0140206B1 (https=)
JP (1) JPS6081836A (https=)
DE (1) DE3469067D1 (https=)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4613771A (en) * 1984-04-18 1986-09-23 Burroughs Corporation Integrated circuit having three power bases and proportioned parasitic resistive and capacitive coupling to reduce output noise
US4596940A (en) * 1984-04-19 1986-06-24 Hewlett-Packard Company Three state differential ECL bus driver
US4644265A (en) * 1985-09-03 1987-02-17 International Business Machines Corporation Noise reduction during testing of integrated circuit chips
EP0233634A3 (de) * 1986-02-20 1989-07-26 Siemens Aktiengesellschaft Verfahren zum Funktionstest von digitalen Bausteinen
KR100224731B1 (ko) 1997-06-23 1999-10-15 윤종용 논리 디바이스 테스트 장치 및 방법
US6000050A (en) * 1997-10-23 1999-12-07 Synopsys, Inc. Method for minimizing ground bounce during DC parametric tests using boundary scan register
JP2000025519A (ja) 1998-07-14 2000-01-25 Kayama Yuki 車両用サイドミラー
DE10038616B4 (de) * 2000-08-08 2012-07-12 Atmel Automotive Gmbh Verfahren und Anordnung zur Störunterdrückung in einer Empfängerschaltung
EP1475274B1 (en) * 2003-05-06 2011-08-31 Mitsubishi Electric Information Technology Centre Europe B.V. Seat occupant monitoring system and method

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2121330C3 (de) * 1971-04-30 1974-10-17 Ludwig 6369 Dortelweil Illian Verfahren und Schaltungsanordnung zum Prüfen digital arbeitender elektronischer Geräte und ihrer Bauteile
US4000460A (en) * 1974-07-01 1976-12-28 Xerox Corporation Digital circuit module test system
US4070565A (en) * 1976-08-18 1978-01-24 Zehntel, Inc. Programmable tester method and apparatus
CA1079804A (en) * 1977-03-14 1980-06-17 Ibm Canada Limited - Ibm Canada Limitee Voltage sequencing circuit for sequencing voltage to an electrical device
US4204633A (en) * 1978-11-20 1980-05-27 International Business Machines Corporation Logic chip test system with path oriented decision making test pattern generator
JPS5621419A (en) * 1979-07-31 1981-02-27 Nec Corp Logical operation circuit
JPS5760865A (en) * 1980-09-30 1982-04-13 Nec Corp Integrated circuit device
US4357703A (en) * 1980-10-09 1982-11-02 Control Data Corporation Test system for LSI circuits resident on LSI chips
JPS5787150A (en) * 1980-11-19 1982-05-31 Matsushita Electric Ind Co Ltd Large-scale integrated circuit
US4398106A (en) * 1980-12-19 1983-08-09 International Business Machines Corporation On-chip Delta-I noise clamping circuit
US4394588A (en) * 1980-12-30 1983-07-19 International Business Machines Corporation Controllable di/dt push/pull driver
US4439858A (en) * 1981-05-28 1984-03-27 Zehntel, Inc. Digital in-circuit tester
DE3232199C1 (de) * 1982-08-30 1983-12-29 Siemens AG, 1000 Berlin und 8000 München Schaltungsanordnung in ECL-Schaltungstechnik
US4499579A (en) * 1983-03-10 1985-02-12 Honeywell Information Systems Inc. Programmable logic array with dynamic test capability in the unprogrammed state

Also Published As

Publication number Publication date
EP0140206B1 (en) 1988-01-27
US4553049A (en) 1985-11-12
JPH0533540B2 (https=) 1993-05-19
EP0140206A1 (en) 1985-05-08
JPS6081836A (ja) 1985-05-09

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee