DE3460915D1 - Integrated circuit device and method of diagnosing the same - Google Patents

Integrated circuit device and method of diagnosing the same

Info

Publication number
DE3460915D1
DE3460915D1 DE8484100876T DE3460915T DE3460915D1 DE 3460915 D1 DE3460915 D1 DE 3460915D1 DE 8484100876 T DE8484100876 T DE 8484100876T DE 3460915 T DE3460915 T DE 3460915T DE 3460915 D1 DE3460915 D1 DE 3460915D1
Authority
DE
Germany
Prior art keywords
diagnosing
same
integrated circuit
circuit device
integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE8484100876T
Other languages
English (en)
Inventor
Ikuro Masuda
Hideo Maejima
Terumine Hayashi
Kazumi Hatayama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Application granted granted Critical
Publication of DE3460915D1 publication Critical patent/DE3460915D1/de
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318558—Addressing or selecting of subparts of the device under test
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318516—Test of programmable logic devices [PLDs]

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
DE8484100876T 1983-02-04 1984-01-27 Integrated circuit device and method of diagnosing the same Expired DE3460915D1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58016045A JPH07119789B2 (ja) 1983-02-04 1983-02-04 半導体集積回路装置及びその診断方法

Publications (1)

Publication Number Publication Date
DE3460915D1 true DE3460915D1 (en) 1986-11-13

Family

ID=11905596

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8484100876T Expired DE3460915D1 (en) 1983-02-04 1984-01-27 Integrated circuit device and method of diagnosing the same

Country Status (4)

Country Link
US (1) US4613970A (de)
EP (1) EP0118704B1 (de)
JP (1) JPH07119789B2 (de)
DE (1) DE3460915D1 (de)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH073865B2 (ja) * 1984-08-07 1995-01-18 富士通株式会社 半導体集積回路及び半導体集積回路の試験方法
US4739250A (en) * 1985-11-20 1988-04-19 Fujitsu Limited Semiconductor integrated circuit device with test circuit
US4749947A (en) * 1986-03-10 1988-06-07 Cross-Check Systems, Inc. Grid-based, "cross-check" test structure for testing integrated circuits
JPS6329276A (ja) * 1986-07-23 1988-02-06 Hitachi Ltd 論理ｌｓｉ
US4996659A (en) * 1986-08-20 1991-02-26 Hitachi, Ltd. Method of diagnosing integrated logic circuit
US4877382A (en) * 1986-08-22 1989-10-31 Copeland Corporation Scroll-type machine with axially compliant mounting
US4767293A (en) * 1986-08-22 1988-08-30 Copeland Corporation Scroll-type machine with axially compliant mounting
US5365165A (en) * 1986-09-19 1994-11-15 Actel Corporation Testability architecture and techniques for programmable interconnect architecture
US5477165A (en) * 1986-09-19 1995-12-19 Actel Corporation Programmable logic module and architecture for field programmable gate array device
JP2556017B2 (ja) * 1987-01-17 1996-11-20 日本電気株式会社 論理集積回路
US4876501A (en) * 1987-04-13 1989-10-24 Prime Computer, Inc. Method and apparatus for high accuracy measurment of VLSI components
US5065090A (en) * 1988-07-13 1991-11-12 Cross-Check Technology, Inc. Method for testing integrated circuits having a grid-based, "cross-check" te
US5157627A (en) * 1990-07-17 1992-10-20 Crosscheck Technology, Inc. Method and apparatus for setting desired signal level on storage element
US5179534A (en) * 1990-10-23 1993-01-12 Crosscheck Technology, Inc. Method and apparatus for setting desired logic state at internal point of a select storage element
US5528600A (en) * 1991-01-28 1996-06-18 Actel Corporation Testability circuits for logic arrays
US5206862A (en) * 1991-03-08 1993-04-27 Crosscheck Technology, Inc. Method and apparatus for locally deriving test signals from previous response signals
US5230001A (en) * 1991-03-08 1993-07-20 Crosscheck Technology, Inc. Method for testing a sequential circuit by splicing test vectors into sequential test pattern
US5495486A (en) * 1992-08-11 1996-02-27 Crosscheck Technology, Inc. Method and apparatus for testing integrated circuits
US5799021A (en) * 1994-10-28 1998-08-25 Duet Technologies, Inc. Method for direct access test of embedded cells and customization logic
JP3606525B2 (ja) 2002-12-05 2005-01-05 沖電気工業株式会社 スキャンテスト回路
US7383480B2 (en) * 2004-07-22 2008-06-03 International Business Machines Corporation Scanning latches using selecting array
JP2007132297A (ja) * 2005-11-11 2007-05-31 Sanden Corp スクロール型流体機械

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4140967A (en) * 1977-06-24 1979-02-20 International Business Machines Corporation Merged array PLA device, circuit, fabrication method and testing technique
AU530415B2 (en) * 1978-06-02 1983-07-14 International Standard Electric Corp. Integrated circuits
JPS5615530A (en) * 1979-07-19 1981-02-14 Toshiba Corp Manufacture of color picture tube
US4404519A (en) * 1980-12-10 1983-09-13 International Business Machine Company Testing embedded arrays in large scale integrated circuits
US4503386A (en) * 1982-04-20 1985-03-05 International Business Machines Corporation Chip partitioning aid (CPA)-A structure for test pattern generation for large logic networks
US4527115A (en) * 1982-12-22 1985-07-02 Raytheon Company Configurable logic gate array
US4503387A (en) * 1982-12-30 1985-03-05 Harris Corporation A.C. Testing of logic arrays

Also Published As

Publication number Publication date
EP0118704B1 (de) 1986-10-08
US4613970A (en) 1986-09-23
JPS59142481A (ja) 1984-08-15
EP0118704A1 (de) 1984-09-19
JPH07119789B2 (ja) 1995-12-20

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee