DE3337529A1 - Electronic parallel adder-subtractor mechanism using BCD-8421 Code - Google Patents

Abstract

Published without abstract.

Description

Electronic parallel eddier subtracter

in BCD-8421 code The subject of the invention is an electronic one Parallel adder subtracter in the BCD-8421 code, in which only B5D-O numbers are entered and in which all result numbers are BCD-O-coded and that accordingly the above designation can be switched from addition to subtraction and from subtraction can be switched to addition. In the case of the present parallel adding-subtracting mechanism when adding the basic number 6 (LHHL) is added in an additional addition (in every decade) and thus on the one hand avoided one of the two summands or the first summand has to be entered BCD-6-coded and, on the other hand, avoided that the tetrad adder sub: brahierer with an input adder circuit for the basic number 6 (LHHL) must be provided. In the present description BCD numbers, which are not raised by the number 6 (LHHL) and also not by one other number are raised, referred to as BCD-O numbers. BCD numbers, which around The number 6 (SHEL) raised will be used in the present specification as BCD-6 numbers designated. Accordingly, excess-3 encoded numbers are used in the present specification referred to as BCD-3 numbers. As a result of the fact that when adding the memory rows 2 and 3 are always required, this parallel-adder-subtractor is only available as a Type C possible.

IL Figure 1 is a decade of the parallel 4ddier-subtracter type C 1 shown. In Figure 2 is a decade of the parallel-Aduier-Subtrahierweras Type ~ 2 shown. In Figure 3, the tetrad adlier subtracter 1 a is shown, which consists of the main circuit 4 and the correction circuit 5 a. In figure 4 the tetrad # adder-subtracter 1 b is shown, which is from the main circuit 4 and the correction circuit 5 b consists. In Figure 5 is the additional circuit 6 shown. In Figure 6, the control diagram A 1 is shown; after this The present parallel-adding-subtracting unit then becomes the first control diagram activated when one addend is present at the A inputs and the other addend is present at the B inputs. In Figure 7, the control diagram A 2 is shown; the present parallel-adding-subtracting unit is based on this control diagram then activated when a summand is added to the previous result number or is added to the number 0 (LLLL) (in every decade); in this case, each only brought one summand to the system, but not at the B entrances, but at the A inputs. In Figure 8, the control diagram A 3 is shown; according to this control diagram the present parallel-adding-subtracting unit is activated when a summand is applied to the A inputs and the other summand is applied to the B inputs or if a summand adds number to the number 0 (zero) or to the previous result will; in the first case no number may be stored in memory row 3; in the latter case there must be no number at the B inputs. In Figure 9 this is Control diagram S 1 shown; according to this control diagram, the present Parallel adder subtracter activated when the minuend at the B inputs and the subtrahend at the A inputs. In Figure 10 is the control diagram S 2 shown; according to this control diagram, the present is parallel-adding-subtracting then activated when the previous result number is the minuend and the subtrahend is present at the A inputs.

The control diagram S 3 is shown in FIG. 11; after this Control diagram, the present parallel adding-subtracting unit is then controlled, when the minuend is applied to the B inputs and the subtrahend to the A inputs or if the preceding result number is the jvlinuend and the subtrahend is on is applied to the A inputs; in the first case, a number may be in the memory row 3 be stored; in the latter case, the 3 - ## inputs must not be followed by a number.

One decade of the parallel add-subtracter type 5 1 (Figure 1) consists of the switchable tetrad adder-subtracter 1 a and the memory rows 2 and 3 and the other parts and lines. The tetrad adder-subtracter 1 a consists of the main circuit 4, which can be switched from addition to subtraction is and can be switched from subtraction to addition and the correction circuit 5 a and the additional circuit 6 and the additional AND circuit 7. The main circuit 4 is shown in detail in FIG. 3 and thus consists of the full adders-subtractors 31 to 34. The correction circuit 5 a is a subtracting circuit for the number 6 (LRHL) and consists of the half subtracter 35 and the full subtracter 36 and the remainder circuit 37; this circuit is also shown in FIG. The additional circuit 6 is shown in FIG. The inputs have the designations A 1 to A 4 and B 1 to B 4. The result outputs have the designations D 1 to D 4. The decade carry input is labeled x and the decade carry output is labeled y. The entrances A 1 and B1 and the output D 1 have the value 1. The inputs A 2 and B 2 and the output D 2 have the valency 2. The inputs A 3 and B 3 and the output D 3 have the valency 4. The inputs A 4 and B 4 and the output D 4 have the Value 8.

A decade of the parallel add-subtracter type ~ 2 Figure 2) shows the difference in comparison with the decade shown in Figure 1, that instead of the correction circuit 5 a another Korrexturs ^ attitude 5 b arranged is.

This correction circuit 5 b is an adding circuit for the number 10 (HLHL). The number 6 (SHHL) is subtracted here by the fact that the number 10 (HOHL) is added and the related tetrad carry is not processed will.

The mode of operation of the parallel add-subtracter type C 1, consisting from a small, medium or large number of decades according to FIG. 1 when adding as follows: The setting for addition is made by creating of H potential to the continuous control line f, the continuous control line e, which is controlled by the Steuerleitwag f via a negative circuit t, potential. Then one of the two summands at the A inputs becomes System brought and the other summand at the B inputs and this parallel add-subtracter controlled according to Figure 6. The first round will be the one at the B entrances The base number 6 (LHHL) is added to the attached summands in every decade, which means that the at the B inputs Bt ^ D-O-coded summand BCD-6-coded in the memory rows 2 and 3 is saved. During the second pass, the also only BCD-O-coded, Another summand to the now BCD-6 coded first, present at the A inputs Summands added, whereby in the decades which have no De # aden carry-over exit, the number 6 (LXEL) is automatically subtracted by the corresponding Korrestur circuit will. The result number is automatically BCD-O-coded. With the second addition method According to FIG. 7, only one summand comes to the system (at the A inputs) and becomes this parallel-adding-subtracting mechanism according to FIG. 7 through-controlled. Here so the first summand is added to the number 0 and thus the first summand only in memory rows 2 and 3 are entered. If then the second summand at the A inputs is brought to the plant and this parallel-adding-subtracting again according to FIG 7 is controlled, the first round of every decade is played the number 6 (LHHL) is added and then in the second round the second summand to the previous one Addition result number, which is the now BCD-6-coded first summand. Even in the decade, which do not have a decade-Uberbra exit, will be automatic the number 6 (LE7L) is subtracted again, which is also the result number in this case is not 35D-6 coded, but only B2, D-0 coded.

The mode of operation of this parallel-adding-subtracting unit results from subtracting as follows: The setting for subtraction is made by applying L potential to the continuous control line f, the continuous control line e, which is controlled by the control line f via a negative circuit, at H potential lies. Then the minuend is attached to the B-entrances and the subtrahend at the A inputs and this parallel Uddier subtracter according to FIG. Here, in the decades that have a decade-to-carry outflow, automatically subtracts the number 6 (MEHL), whereby the subtraction result number is automatically BCD-O-coded is.

If a previous one is still stored in memory rows 2 and 3 Result number is processed as a minuend, this parallel adder-subtracter controlled according to FIG. The subtrahend must also be at the outlets be brought to the facility.

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Claims (4)

Claims 1 Electronic Paraliel-Addier-Subtrahierwerk im BCD-8421 code in which the number 6 (SHHL) is subtracted when added in those decades that have a decade carry-over exit and with subtraction in those Decades the number 6 (SHHL) is subtracted, which have a decade carry-over exit and in which thus all result numbers occur in BGI) -O-coded and their decades have a tetrad adder-subtracter consisting of a main circuit (4) and a correction circuit (5 a) and an additional circuit (6) consists thereby characterized in that it is designed so that all numbers entered BCD-O-coded can be. 2) Electronic parallel-adding-subtracting mechanism according to claim 1, characterized in that the basic number 6 (LEEL) required for adding in is added every decade by means of an additional addition. 3) Electronic Barallel-Adaier subtracter according to claim 1 and 2, characterized in that the error-free control of the correction circuit (5 a), which is a subtracting circuit for the number 6 (LHHL), thereby enables is that an additional AND circuit (7) is arranged in each decade, which is pre-activated by a continuous control line (g). 4) Electronic parallel add-subtracter according to claim 1 to 3, characterized in that in the case of type C 2 instead of the correction circuits (5 a) other correction circuits (5 b) are arranged, which upon activation additively subtract the number 6 (HET,) by adding the number 10 (XLEL) and the related tetrad transfer is not processed.