DE3272436D1 - Method of making a monolithic integrated circuit with at least one isolated gate field effect transistor and one bipolar transistor - Google Patents

Method of making a monolithic integrated circuit with at least one isolated gate field effect transistor and one bipolar transistor

Info

Publication number
DE3272436D1
DE3272436D1 DE8282103910T DE3272436T DE3272436D1 DE 3272436 D1 DE3272436 D1 DE 3272436D1 DE 8282103910 T DE8282103910 T DE 8282103910T DE 3272436 T DE3272436 T DE 3272436T DE 3272436 D1 DE3272436 D1 DE 3272436D1
Authority
DE
Germany
Prior art keywords
making
integrated circuit
field effect
gate field
monolithic integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE8282103910T
Other languages
German (de)
English (en)
Inventor
Lothar Dipl Phys Blossfeld
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TDK Micronas GmbH
ITT Inc
Original Assignee
Deutsche ITT Industries GmbH
ITT Industries Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Deutsche ITT Industries GmbH, ITT Industries Inc filed Critical Deutsche ITT Industries GmbH
Application granted granted Critical
Publication of DE3272436D1 publication Critical patent/DE3272436D1/de
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/20—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0107—Integrating at least one component covered by H10D12/00 or H10D30/00 with at least one component covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating IGFETs with BJTs
    • H10D84/0109—Integrating at least one component covered by H10D12/00 or H10D30/00 with at least one component covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating IGFETs with BJTs the at least one component covered by H10D12/00 or H10D30/00 being a MOS device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
DE8282103910T 1982-05-06 1982-05-06 Method of making a monolithic integrated circuit with at least one isolated gate field effect transistor and one bipolar transistor Expired DE3272436D1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP82103910A EP0093786B1 (de) 1982-05-06 1982-05-06 Verfahren zum Herstellen einer planaren monolithisch integrierten Festkörperschaltung mit mindestens einem Isolierschicht-Feldeffekttransistor und mit mindestens einem Bipolartransistor

Publications (1)

Publication Number Publication Date
DE3272436D1 true DE3272436D1 (en) 1986-09-11

Family

ID=8189022

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8282103910T Expired DE3272436D1 (en) 1982-05-06 1982-05-06 Method of making a monolithic integrated circuit with at least one isolated gate field effect transistor and one bipolar transistor

Country Status (4)

Country Link
US (1) US4503603A (https=)
EP (1) EP0093786B1 (https=)
JP (1) JPS5941864A (https=)
DE (1) DE3272436D1 (https=)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4673965A (en) * 1983-02-22 1987-06-16 General Motors Corporation Uses for buried contacts in integrated circuits
GB2172744B (en) * 1985-03-23 1989-07-19 Stc Plc Semiconductor devices
GB8507624D0 (en) * 1985-03-23 1985-05-01 Standard Telephones Cables Ltd Semiconductor devices
CA1258320A (en) * 1985-04-01 1989-08-08 Madhukar B. Vora Small contactless ram cell
JPS61287159A (ja) * 1985-06-13 1986-12-17 Oki Electric Ind Co Ltd Ｂｉ−ＣＭＯＳ半導体ＩＣ装置の製造方法
DE3680520D1 (de) * 1986-03-22 1991-08-29 Itt Ind Gmbh Deutsche Verfahren zum herstellen einer monolithisch integrierten schaltung mit mindestens einem bipolaren planartransistor.
KR890004420B1 (ko) * 1986-11-04 1989-11-03 삼성반도체통신 주식회사 반도체 바이 씨 모오스장치의 제조방법
EP0270703B1 (de) * 1986-12-12 1991-12-18 Deutsche ITT Industries GmbH Verfahren zum Herstellen einer monolithisch integrierten Schaltung mit mindestens einem bipolaren Planartransistor
JPS63239856A (ja) * 1987-03-27 1988-10-05 Hitachi Ltd 半導体集積回路装置及びその製造方法
JPS63304657A (ja) * 1987-06-04 1988-12-12 Fujitsu Ltd 半導体装置の製造方法
US4958213A (en) * 1987-12-07 1990-09-18 Texas Instruments Incorporated Method for forming a transistor base region under thick oxide
US5179031A (en) * 1988-01-19 1993-01-12 National Semiconductor Corporation Method of manufacturing a polysilicon emitter and a polysilicon gate using the same etch of polysilicon on a thin gate oxide
US5124817A (en) * 1988-01-19 1992-06-23 National Semiconductor Corporation Polysilicon emitter and a polysilicon gate using the same etch of polysilicon on a thin gate oxide
US5001081A (en) * 1988-01-19 1991-03-19 National Semiconductor Corp. Method of manufacturing a polysilicon emitter and a polysilicon gate using the same etch of polysilicon on a thin gate oxide
US4918026A (en) * 1989-03-17 1990-04-17 Delco Electronics Corporation Process for forming vertical bipolar transistors and high voltage CMOS in a single integrated circuit chip
US5171702A (en) * 1989-07-21 1992-12-15 Texas Instruments Incorporated Method for forming a thick base oxide in a BiCMOS process
IT1241050B (it) * 1990-04-20 1993-12-29 Cons Ric Microelettronica Processo di formazione di una regione sepolta di drain o di collettore in dispositivi monolitici a semiconduttore.
US5013671A (en) * 1990-06-20 1991-05-07 Texas Instruments Incorporated Process for reduced emitter-base capacitance in bipolar transistor
US5124271A (en) * 1990-06-20 1992-06-23 Texas Instruments Incorporated Process for fabricating a BiCMOS integrated circuit
US5082796A (en) * 1990-07-24 1992-01-21 National Semiconductor Corporation Use of polysilicon layer for local interconnect in a CMOS or BiCMOS technology incorporating sidewall spacers
US6861303B2 (en) * 2003-05-09 2005-03-01 Texas Instruments Incorporated JFET structure for integrated circuit and fabrication method
US8362564B2 (en) 2010-08-20 2013-01-29 Intersil Americas Inc. Isolated epitaxial modulation device
CN109390217B (zh) * 2017-08-09 2020-09-25 华邦电子股份有限公司 光掩膜及半导体装置的形成方法

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4058887A (en) * 1971-02-19 1977-11-22 Ibm Corporation Method for forming a transistor comprising layers of silicon dioxide and silicon nitride
JPS4929582A (https=) * 1972-07-14 1974-03-16
JPS5094886A (https=) * 1973-12-22 1975-07-28
JPS5624384B2 (https=) * 1974-01-30 1981-06-05
JPS5912021B2 (ja) * 1975-09-10 1984-03-19 株式会社日立製作所 半導体装置の製造方法
FR2358748A1 (fr) * 1976-07-15 1978-02-10 Radiotechnique Compelec Procede d'autoalignement des elements d'un dispositif semi-conducteur et dispositif realise suivant ce procede
US4231051A (en) * 1978-06-06 1980-10-28 Rockwell International Corporation Process for producing minimal geometry devices for VSLI applications utilizing self-aligned gates and self-aligned contacts, and resultant structures
US4314267A (en) * 1978-06-13 1982-02-02 Ibm Corporation Dense high performance JFET compatible with NPN transistor formation and merged BIFET
US4325180A (en) * 1979-02-15 1982-04-20 Texas Instruments Incorporated Process for monolithic integration of logic, control, and high voltage interface circuitry
JPS567463A (en) * 1979-06-29 1981-01-26 Hitachi Ltd Semiconductor device and its manufacture
US4311532A (en) * 1979-07-27 1982-01-19 Harris Corporation Method of making junction isolated bipolar device in unisolated IGFET IC
CA1151295A (en) * 1979-07-31 1983-08-02 Alan Aitken Dual resistivity mos devices and method of fabrication
US4299024A (en) * 1980-02-25 1981-11-10 Harris Corporation Fabrication of complementary bipolar transistors and CMOS devices with poly gates
US4295266A (en) * 1980-06-30 1981-10-20 Rca Corporation Method of manufacturing bulk CMOS integrated circuits
US4362574A (en) * 1980-07-09 1982-12-07 Raytheon Company Integrated circuit and manufacturing method
US4373253A (en) * 1981-04-13 1983-02-15 National Semiconductor Corporation Integrated CMOS process with JFET

Also Published As

Publication number Publication date
EP0093786B1 (de) 1986-08-06
JPH0558265B2 (https=) 1993-08-26
JPS5941864A (ja) 1984-03-08
EP0093786A1 (de) 1983-11-16
US4503603A (en) 1985-03-12

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8320 Willingness to grant licences declared (paragraph 23)
8339 Ceased/non-payment of the annual fee