DE3171252D1 - Method for making an electrical contact to a silicon substrate through a relatively thin layer of silicon dioxide on the surface of the substrate and method for making a field effect transistor - Google Patents

Method for making an electrical contact to a silicon substrate through a relatively thin layer of silicon dioxide on the surface of the substrate and method for making a field effect transistor

Info

Publication number
DE3171252D1
DE3171252D1 DE8181109152T DE3171252T DE3171252D1 DE 3171252 D1 DE3171252 D1 DE 3171252D1 DE 8181109152 T DE8181109152 T DE 8181109152T DE 3171252 T DE3171252 T DE 3171252T DE 3171252 D1 DE3171252 D1 DE 3171252D1
Authority
DE
Germany
Prior art keywords
making
substrate
field effect
electrical contact
effect transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE8181109152T
Other languages
English (en)
Inventor
Robert Forbell Bartholomew
Paul Louis Garbarino
James Robert Gardiner
Martin Revitz
Joseph Francis Shepard
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE3171252D1 publication Critical patent/DE3171252D1/de
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28525—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising semiconducting material

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
DE8181109152T 1980-12-05 1981-10-29 Method for making an electrical contact to a silicon substrate through a relatively thin layer of silicon dioxide on the surface of the substrate and method for making a field effect transistor Expired DE3171252D1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/213,526 US4341009A (en) 1980-12-05 1980-12-05 Method for making an electrical contact to a silicon substrate through a relatively thin layer of silicon dioxide on the surface of the substrate

Publications (1)

Publication Number Publication Date
DE3171252D1 true DE3171252D1 (en) 1985-08-08

Family

ID=22795448

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8181109152T Expired DE3171252D1 (en) 1980-12-05 1981-10-29 Method for making an electrical contact to a silicon substrate through a relatively thin layer of silicon dioxide on the surface of the substrate and method for making a field effect transistor

Country Status (4)

Country Link
US (1) US4341009A (de)
EP (1) EP0054163B1 (de)
JP (1) JPS5797679A (de)
DE (1) DE3171252D1 (de)

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US4403394A (en) * 1980-12-17 1983-09-13 International Business Machines Corporation Formation of bit lines for ram device
US4397076A (en) * 1981-09-14 1983-08-09 Ncr Corporation Method for making low leakage polycrystalline silicon-to-substrate contacts
JPH0618213B2 (ja) * 1982-06-25 1994-03-09 松下電子工業株式会社 半導体装置の製造方法
US4464824A (en) * 1982-08-18 1984-08-14 Ncr Corporation Epitaxial contact fabrication process
JPS59201461A (ja) * 1983-04-28 1984-11-15 Toshiba Corp 読み出し専用半導体記憶装置およびその製造方法
JPS60163455A (ja) * 1984-02-03 1985-08-26 Toshiba Corp 読み出し専用記憶装置及びその製造方法
US4962053A (en) * 1987-01-30 1990-10-09 Texas Instruments Incorporated Bipolar transistor fabrication utilizing CMOS techniques
US5179031A (en) * 1988-01-19 1993-01-12 National Semiconductor Corporation Method of manufacturing a polysilicon emitter and a polysilicon gate using the same etch of polysilicon on a thin gate oxide
US5001081A (en) * 1988-01-19 1991-03-19 National Semiconductor Corp. Method of manufacturing a polysilicon emitter and a polysilicon gate using the same etch of polysilicon on a thin gate oxide
US5124817A (en) * 1988-01-19 1992-06-23 National Semiconductor Corporation Polysilicon emitter and a polysilicon gate using the same etch of polysilicon on a thin gate oxide
US4957878A (en) * 1988-05-02 1990-09-18 Micron Technology, Inc. Reduced mask manufacture of semiconductor memory devices
US4948745A (en) * 1989-05-22 1990-08-14 Motorola, Inc. Process for elevated source/drain field effect structure
EP0452720A3 (en) * 1990-04-02 1994-10-26 Nat Semiconductor Corp A semiconductor structure and method of its manufacture
US5082796A (en) * 1990-07-24 1992-01-21 National Semiconductor Corporation Use of polysilicon layer for local interconnect in a CMOS or BiCMOS technology incorporating sidewall spacers
JPH0685204A (ja) * 1992-09-02 1994-03-25 Fujitsu Ltd 半導体装置の製造方法
JPH08255907A (ja) * 1995-01-18 1996-10-01 Canon Inc 絶縁ゲート型トランジスタ及びその製造方法
JP3498764B2 (ja) * 1995-04-14 2004-02-16 松下電器産業株式会社 多結晶シリコン膜のエッチング方法
US5525552A (en) * 1995-06-08 1996-06-11 Taiwan Semiconductor Manufacturing Company Method for fabricating a MOSFET device with a buried contact
US5629235A (en) * 1995-07-05 1997-05-13 Winbond Electronics Corporation Method for forming damage-free buried contact
US5691250A (en) * 1996-08-29 1997-11-25 Taiwan Semiconductor Manufacturing Company, Ltd Method of forming a metal contact to a novel polysilicon contact extension
US6759282B2 (en) * 2001-06-12 2004-07-06 International Business Machines Corporation Method and structure for buried circuits and devices
EP2095100B1 (de) 2006-11-22 2016-09-21 President and Fellows of Harvard College Verfahren zum Betreiben eines Nanodraht-Feldeffekttransistorsensors
US20080286967A1 (en) * 2007-05-18 2008-11-20 Atmel Corporation Method for fabricating a body to substrate contact or topside substrate contact in silicon-on-insulator devices
US8211774B2 (en) * 2009-09-18 2012-07-03 Vanguard International Semiconductor Corporation Method for forming semiconductor structure
US9297796B2 (en) 2009-09-24 2016-03-29 President And Fellows Of Harvard College Bent nanowires and related probing of species

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4991583A (de) * 1972-12-30 1974-09-02
CA1001771A (en) * 1973-01-15 1976-12-14 Fairchild Camera And Instrument Corporation Method of mos transistor manufacture and resulting structure
JPS592191B2 (ja) * 1974-05-11 1984-01-17 松下電子工業株式会社 半導体装置用電極の製造方法
JPS5192186A (en) * 1975-02-10 1976-08-12 mos shusekikairono seizohoho
US4045594A (en) * 1975-12-31 1977-08-30 Ibm Corporation Planar insulation of conductive patterns by chemical vapor deposition and sputtering
US4075045A (en) * 1976-02-09 1978-02-21 International Business Machines Corporation Method for fabricating FET one-device memory cells with two layers of polycrystalline silicon and fabrication of integrated circuits containing arrays of the memory cells charge storage capacitors utilizing five basic pattern deliberating steps
US4013489A (en) * 1976-02-10 1977-03-22 Intel Corporation Process for forming a low resistance interconnect in MOS N-channel silicon gate integrated circuit
JPS583380B2 (ja) * 1977-03-04 1983-01-21 株式会社日立製作所 半導体装置とその製造方法
US4102733A (en) * 1977-04-29 1978-07-25 International Business Machines Corporation Two and three mask process for IGFET fabrication
US4148133A (en) * 1978-05-08 1979-04-10 Sperry Rand Corporation Polysilicon mask for etching thick insulator
US4180826A (en) * 1978-05-19 1979-12-25 Intel Corporation MOS double polysilicon read-only memory and cell
GB2021862B (en) * 1978-05-26 1982-11-24 Rockwell International Corp Contacting polysilicon electrodes
US4157269A (en) * 1978-06-06 1979-06-05 International Business Machines Corporation Utilizing polysilicon diffusion sources and special masking techniques
CA1131796A (en) * 1979-01-08 1982-09-14 Tarsaim L. Batra Method for fabricating mos device with self-aligned contacts
JPS5599722A (en) * 1979-01-26 1980-07-30 Hitachi Ltd Preparation of semiconductor device
US4272880A (en) * 1979-04-20 1981-06-16 Intel Corporation MOS/SOS Process
US4282648A (en) * 1980-03-24 1981-08-11 Intel Corporation CMOS process

Also Published As

Publication number Publication date
EP0054163B1 (de) 1985-07-03
JPS5797679A (en) 1982-06-17
EP0054163A3 (en) 1983-08-03
US4341009A (en) 1982-07-27
EP0054163A2 (de) 1982-06-23

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee