DE3066955D1 - Signal processor computing arrangement and method of operating said arrangement - Google Patents

Signal processor computing arrangement and method of operating said arrangement

Info

Publication number
DE3066955D1
DE3066955D1 DE8080103546T DE3066955T DE3066955D1 DE 3066955 D1 DE3066955 D1 DE 3066955D1 DE 8080103546 T DE8080103546 T DE 8080103546T DE 3066955 T DE3066955 T DE 3066955T DE 3066955 D1 DE3066955 D1 DE 3066955D1
Authority
DE
Germany
Prior art keywords
arrangement
operating
signal processor
processor computing
computing arrangement
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE8080103546T
Other languages
English (en)
Inventor
Pierre Chevillat
Dieter Maiwald
Hans Peter Kaser
Gottfried Ungerbock
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE3066955D1 publication Critical patent/DE3066955D1/de
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H17/00—Networks using digital techniques
    • H03H17/02—Frequency selective networks
    • H03H17/06—Non-recursive filters
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/10—Complex mathematical operations
    • G06F17/15—Correlation function computation including computation of convolution operations
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
    • G06F7/5443—Sum of products
DE8080103546T 1980-06-24 1980-06-24 Signal processor computing arrangement and method of operating said arrangement Expired DE3066955D1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP80103546A EP0042452B1 (de) 1980-06-24 1980-06-24 Signalprozessorrechneranordnung und Verfahren zum Betrieb der Anordnung

Publications (1)

Publication Number Publication Date
DE3066955D1 true DE3066955D1 (en) 1984-04-19

Family

ID=8186702

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8080103546T Expired DE3066955D1 (en) 1980-06-24 1980-06-24 Signal processor computing arrangement and method of operating said arrangement

Country Status (5)

Country Link
US (1) US4490807A (de)
EP (1) EP0042452B1 (de)
JP (1) JPS5713573A (de)
DE (1) DE3066955D1 (de)
IT (1) IT1167787B (de)

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3144015A1 (de) * 1981-11-05 1983-05-26 Ulrich Prof. Dr. 7500 Karlsruhe Kulisch "schaltungsanordnung und verfahren zur bildung von skalarprodukten und summen von gleitkommazahlen mit maximaler genauigkeit"
JPS58181165A (ja) * 1982-04-16 1983-10-22 Hitachi Ltd ベクトル演算プロセツサ
JPS59122040A (ja) * 1982-12-27 1984-07-14 Sony Corp デイジタル信号処理回路
US4766564A (en) * 1984-08-13 1988-08-23 International Business Machines Corporation Dual putaway/bypass busses for multiple arithmetic units
US4692888A (en) * 1984-10-03 1987-09-08 Advanced Micro Devices, Inc. Method and apparatus for generating and summing the products of pairs of numbers
US4683547A (en) * 1984-10-25 1987-07-28 International Business Machines Corporation Special accumulate instruction for multiple floating point arithmetic units which use a putaway bus to enhance performance
JPH0666900B2 (ja) * 1985-02-05 1994-08-24 日立電子株式会社 映像信号処理装置
JPS6263370A (ja) * 1985-05-15 1987-03-20 Toshiba Corp 演算回路
JPS6222177A (ja) * 1985-07-22 1987-01-30 Oki Electric Ind Co Ltd デジタル信号処理装置
JPS62151976A (ja) * 1985-12-25 1987-07-06 Nec Corp 積和演算回路
US4760544A (en) * 1986-06-20 1988-07-26 Plessey Overseas Limited Arithmetic logic and shift device
CA1252213A (en) * 1986-08-28 1989-04-04 Andrew G. Deczky Digital signal processor with divide function
US20050278512A1 (en) * 1988-12-22 2005-12-15 Ehlig Peter N Context switching devices, systems and methods
SE465393B (sv) * 1990-01-16 1991-09-02 Ericsson Telefon Ab L M Adressprocessor foer en signalprocessor
EP0466997A1 (de) * 1990-07-18 1992-01-22 International Business Machines Corporation Verbesserte digitale Signal-Verarbeitungsarchitektur
US5402452A (en) * 1992-08-25 1995-03-28 Alcatel Network Systems, Inc. Incremental phase smoothing desynchronizer and calculation apparatus
DE69325786T2 (de) * 1992-12-04 2000-02-17 Koninkl Philips Electronics Nv Prozessor für gleichförmige Operationen auf Datenreihenfolgen in entsprechenden parallelen Datenströmen
US5650952A (en) * 1992-12-18 1997-07-22 U.S. Philips Corporation Circuit arrangement for forming the sum of products
DE4242929A1 (de) * 1992-12-18 1994-06-23 Philips Patentverwaltung Schaltungsanordnung zum Bilden der Summe von Produkten
US5509129A (en) * 1993-11-30 1996-04-16 Guttag; Karl M. Long instruction word controlling plural independent processor operations
WO1995027939A1 (en) * 1994-04-07 1995-10-19 Media Vision, Inc. Musical instrument simulation processor
US5822609A (en) * 1995-06-22 1998-10-13 International Business Machines Corporation Processing circuit for performing a convolution computation
US6029267A (en) * 1997-11-25 2000-02-22 Lucent Technologies Inc. Single-cycle, soft decision, compare-select operation using dual-add processor
US6230180B1 (en) * 1998-10-14 2001-05-08 Conexant Systems, Inc. Digital signal processor configuration including multiplying units coupled to plural accumlators for enhanced parallel mac processing
GB2363924A (en) * 2000-06-20 2002-01-09 Virata Ltd Processor for FIR filtering
US6748411B1 (en) 2000-11-20 2004-06-08 Agere Systems Inc. Hierarchical carry-select multiple-input split adder
JP4278317B2 (ja) * 2001-07-05 2009-06-10 富士通マイクロエレクトロニクス株式会社 演算装置および受信装置

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3508038A (en) * 1966-08-30 1970-04-21 Ibm Multiplying apparatus for performing division using successive approximate reciprocals of a divisor
US3748451A (en) * 1970-08-21 1973-07-24 Control Data Corp General purpose matrix processor with convolution capabilities
US3840727A (en) * 1972-10-30 1974-10-08 Amdahl Corp Binary multiplication by addition with non-verlapping multiplier recording
US3805045A (en) * 1972-10-30 1974-04-16 Amdahl Corp Binary carry lookahead adder using redundancy terms
US3840861A (en) * 1972-10-30 1974-10-08 Amdahl Corp Data processing system having an instruction pipeline for concurrently processing a plurality of instructions
GB1476603A (en) * 1975-08-27 1977-06-16 Standard Tleephones Cables Ltd Digital multipliers
FR2413712A1 (fr) * 1977-12-30 1979-07-27 Ibm France Microprocesseur specialise pour le calcul de la somme de produits de deux operandes complexes

Also Published As

Publication number Publication date
IT8122116A0 (it) 1981-06-03
JPS5713573A (en) 1982-01-23
IT1167787B (it) 1987-05-13
EP0042452B1 (de) 1984-03-14
US4490807A (en) 1984-12-25
JPS6125188B2 (de) 1986-06-14
EP0042452A1 (de) 1981-12-30

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Legal Events

Date Code Title Description
8339 Ceased/non-payment of the annual fee