DE3036823A1 - Electronic adder and subtractor for 8421-bcd code - has facility for automatic result correction together with decimal display - Google Patents

Abstract

The parallel adder and subtractor circuit is designed for operation in BCD-8421 code and includes an automatic facility for result correction. Each decade of adder-subtractor circuitry consists of five full adders (VA) and two half adders (VS) for the adder operation. The subtraction function is provided by five full subtractors (VS) and two half subtractors (HS). Outputs are fed to flip-flops (E,F) coupled to a decoder stage (4,5) that provide drive signals for a decimal display. The subtractend is applied to the (B) inputs and the minuend to the (A) inputs.

Description

Electronic adding and subtracting mechanism

im 30I) -8421-Oode with decimal display is the subject of the invention an electronic parallel adding and subtracting mechanism, the feedback lines has one complete tetrad adder and one per decade has full tetrad subtracters. How this parallel adding-and-subtracting mechanism works is also based on the fact that before each first addition in all decades the basic number 6 (LHHL) is added to the memory number zero (LLLL) and before each first subtraction in all decades this basic number is removed again by subtraction. The order of 2 decoding circuits per decade is used in this parallel adding and subtracting unit also avoided by switching to subtraction when displaying, with the maximum number 6 (SHXL) is removed again by automatic subtraction. All Numbers are entered decimal-dual-coded (3CD-8421-coded). The addition carry is also triggered by exceeding the decade memory value 15 and the Subtraction carryover by falling below the decade storage value 0 (zero).

FIG. 1 shows a decade of this parallel adding-and-subtracting unit and in Figure 2 the tetrad adder of this decade, which in Figure 1 by 5 full adders VA and 2 half adders HA is shown and in reality off 12 half adder 10 consists (Figure 2). In Figure 3 is the tetrad subtracter This decade is represented in FIG. 1 by 5 full subtractors VS and 2 half subtractors HS is shown and in reality consists of 12 half-subtractors 20 (Fig 3). In Figure 4, the detail C is shown, which occurs 4 times in each decade. FIG. 5 shows the control circuit for the continuous control lines s and i and in Figure 6 a decimal-dual coding circuit (BCD coding circuit) for converting decimal digits into dual coded decimal digits.

This electronic parallel adding-and-subtracting mechanism does not exist additionally required control unit from an arbitrarily large number of decades Figure 1. Each decade consists of a tetrad adder 1 and 5 full adders VA and 2 half adders HA and a tetrad subtracter 2, which consists of 5 full subtractors VS and 2 half-subtractors HS. In other parts of this there is a decade Parallel adder and subtracter from memory rows E and F, which each consist of 4 Memory flip-flopps 3 and the dual decimal decoder circuit 4, which consists of 10 AND circuits 5 and 4 negative circuits 6. On other parts each decade also consists of one or two decimal-dual coding circuits 12, which is shown in FIG. Each full adder VA is made up of two half adders 10 assembled (Figure 2); each full subtractor VS is made up of two half subtractors 20 assembled (Figure 3).

The mode of operation of this parallel adding-and-subtracting unit for that a corresponding control unit is also required, results as follows: If 2 or more decimal numbers are to be added together, first is a setting to addition is required, whereby the control line s by applying is pre-switched from H potential to the line k. Then follows with little the automatic addition of the basic number 6 (LHHL) to the decade memory value Zero (LLBL) in all decades. This automatic addition of the basic number 6 to the memory value Zero in every decade is achieved by the fact that in every decade at the inputs A 2 and A 3 H potential comes to the plant and that one after the other the control lines e and q are charged with an H-current pulse. So this basic number is 6 (LHHL) stored in memory row F every decade and is therefore available at all B inputs at. Then the first summand is entered via the A inputs, its addition to the basic number (666666) takes place in that one after the other the control lines e and q are fed with an H-current pulse. Further summands are equal Way added. After one or more addition is completed, the line becomes k at L potential placed and thus this arithmetic unit on subtraction switched and the basic number 6 (LitEt) removed by subtraction in all decades. This automatic subtraction of the basic number 6 in all decades is then carried out by that in all decades at the inputs A 2 and A 3 H-potential comes to the plant and that one after the other the control lines e and q are fed with an H-current pulse will. This is followed by the display of the total, with each decoding circuit 4 one Displays the decimal number of the result sum. To perform subtractions lies so the control line k to L potential.

If this addition result sum is not deleted and from this Number (minuend) another number (subtrahend) is subtracted, this is done by that this is also dual-coded (BCD-coded) at the A inputs and then one after the other the control lines e and q with an H-current pulse be charged. Further subtrahends are subtracted in the same way. Here are the intermediate subtraction result numbers at the B inputs and must so that only the respective subtrahend is brought to the system at the A inputs. If the minuend is not a previous addition sum and only subtracts a subtrahend is to be, the minuend comes at the B inputs and the subtrahend at the A inputs to the system and the subtraction also takes place in that one after the other the control lines e and q are fed with an H-current pulse. Since here no basic number is added no basic number has to be subtracted if after the one or multiple subtraction the subtraction result number or final subtraction result number is brought to the display.

If instead of transistors 7 to 9 field effect transistors are more suitable or if only field effect transistors can be used for this purpose instead of the transistors 7 to 9 field effect transistors for use.

Insulating-layer field-effect transistors are very likely for this necessary.

In the versions D of the flip-flopps 3 there are no basic resistors 15 and 16 arranged.

The basic number 6 (LHHL) can only be added via the B inputs, if it is added to the memory value zero (LLLL) or if at the A- # inputs the first summand is present and the memory rows E and F are empty, otherwise There are stored values at the B inputs that are greater than LLLL. The distance (Subtraction) of the basic number 6 in all decades can only be done via the A inputs, because the B inputs are minuend inputs when subtracted.

Claims (4)

Claims Electronic parallel adding and subtracting unit, whose decade memory values are increased by the number 6 (LHHL) before being added and its decade storage values before subtracting to those not raised Stand be lowered, characterized in that each decade with a tetrad adder and a tetrad subtracter is provided. 2) Electronic parallel adding and subtracting mechanism according to claim 1, characterized in that the switch from addition to subtraction by 2 Control lines (s and i) takes place, of which one line (s) the outputs of the tetrad adder (1) controls and a line (i) controls the outputs of the tetrad subtracter (2). 3) Electronic parallel adding and subtracting unit according to claim 1, characterized in that in a special version only one decade Correction-free tetrad adder and a correction-free tetrad subtracter and that the corresponding correction additions as automatic additional additions come out for and that the corresponding correction subtractions as automatic Additional subtractions are carried out. 4) Electronic parallel adding and subtracting unit according to claim 3, characterized in that the decade carry-over potential in additional flip-flopps or other suitable storage elements and in the following Eorrettur addition or correction subtraction via AND circuits the corresponding Controls inputs for the binary number LHHS.