DE3119549A1 - Electronic adder and subtractor in octal/dual code - Google Patents

Abstract

The subject matter of the invention is an electronic parallel adder/subtractor in octal/dual code which also exhibits feedback lines so that the preceding addition sum is immediately present again at the A inputs or B inputs. In the present case, the subtotal sum is present at the B inputs. Thus, a circuit according to Figure 1 which only exhibits three full adders/subtractors (VAS) is required for each octal position. <IMAGE>

Description

Electronic adding and subtracting mechanism

in octal-dual code The subject of the invention is an electronic one Parallel adding-and-subtracting unit in octal-dual code, which also has feedback lines having. The design of this arithmetic unit as a combined adding-and-subtracting unit is also made possible by the use of switchable full adder-subtractors allows, which can be used here in an ideal way because it is here there is no carry-over correction. So with this adding-and-subtracting mechanism also combined full adder-subtractors according to P 30 35 275.9 and P 31 Ol 992.7 for use, which are shown in P 31 Ci 992.7 in FIG.

In Figure 1, an octad of this octal-parallel adder is shown and in FIG. 2 the associated octad adder-subtracter, which consists of 3 full adder-subtractors VAS, each of which consists of 2 half-adder-subtracters 1. In figure A "decade" of a hexadecimal-parallel adder is shown in FIG. 3 and in FIG 4 the associated adder-subtractor, which consists of 4 full adder-subtractors. Detail 0 is shown in FIG. 5 and an octal-dual coding circuit is shown in FIG. FIG. 7 shows the pulse diagram for the control lines p and q.

The electronic octal-parallel add-and-subtract # (Fig 1 and 2) consists of a small or large number of octad circuits as shown in the figure 1, because an octad circuit as shown in Figure 1 is required for each octal digit is. Each decade consists of 3 full adder-subtractors VAS, each consisting of two half-adder-subtractors 1 and 2 rows of memory flip-flopps E and F with 3 memory flip-flops each 2. Part 3 is the detoding circuit, which consists of 8 AND circuits with 3 inputs each consists. Entering the Digits (octal digits) are made using octal-dual coding circuits according to FIG. 6 or, if these numbers are already stored in binary form, via shift registers. The additionally required tail unit is not shown and not described.

The mode of operation of this combined parallel adding and subtracting unit when adding results as follows: The setting for addition is made by that the control line s, which, like the control lines i, p and q, crosses all octades, is applied to H potential, whereby the control line i via a negating circuit Has L potential and thus the AND circuits x in circuits 1 are pre-activated and the AND circuits y at the control input have L potential and therefore not are pre-controlled. Then the first summand is dual coded (every octal digit gives 3 binary digits) at the B inputs and the second summand at the A inputs, so that at the outputs of the full adder-subtractor VAS the Sum result number is available as a potential series. The output sides of the full adder-subtracter have the designations a, b, c. Then this total result number is entered into the storage row E by charging the control line p with an H-current pulse. The total result number is thus stored in the memory row E. Then it takes place the input of this total result number into the memory row F by charging the control line q with an H-current pulse. This is the total result number also stored in the memory bank F and is through the Dekodierschalturigen 3 is displayed and is also available as a series of potentials at the B inputs at. If a further summand is to be added, this comes at the A inputs to the system, which means that the previous total result number is available at the B inputs and the third summand at the A inputs. The addition of the third addend takes place then also by the fact that successively with a sufficient time interval the control lines p and q are fed with an H-current pulse. The addition addition further summands are made in the same way, with the previous sum total is automatically applied to the 3 inputs.

The mode of operation of this combined parallel adding and subtracting unit when subtracting, the result is as follows: The setting for subtraction is made in that the control line s is connected to B potential, whereby the control line i has H potential via its negating circuit and thus in circuits 1 the AND circuits y are pre-activated and the AND circuits x at the control input Have B potential and are therefore not pre-activated. Then the minuend becomes dual coded at the B-inputs and brought the subtrahend to the A-inputs, with which the subtraction result at the outputs of the full adder-subtractor VAS number is available as a potential series. This subtraction result number is then entered into the storage row E by charging the control line p with an H-current pulse. The subtraction result number is thus stored in the memory row E. then this subtraction result number is entered in the memory row F by The control line q is fed with an H current pulse. This is the subtraction result number is also stored in the memory bank F and is used by the decoding circuits 3 is displayed and is also available as a series of potentials at the B inputs at. If another subtrahend subtracts away from this subtraction result number is to be, this comes to the system at the A-inputs, which means at the B-inputs the previous subtraction result number is applied and the second at the A inputs Subtrahend. The second subtrahend is then also subtracted by that the control lines follow one another with a sufficient time interval p and q are fed with an H-current pulse. The away subtraction of further Subtracting is done in the same way, always using the previous subtraction result number is present at the 3 inputs.

By switching to subtraction you get a previous sum result count a minuend and by switching to addition a previous subtraction result number first summand. The feedback to the B inputs takes place via the lines h.

Instead of the memory flip-flopps shown in FIG memory b'lipp flopps with field effect transistors are also used, which too instead of the resistors have 6 transistors (field effect transistors).

The operating voltage supply line has the designation k and the neutral line the designation 0.

In Figures 1 to 4, the carry input has the designation m and the carry-over output has the designation n.

L e r s e i t e

Claims (4)

Claims for an electronic parallel adding-and-subtracting mechanism in octal # ual code, characterized in that there are 3 switchable full adder-subtractors per octade having. 2) Electronic Paral le l-ud ier-und -Subtrahierwerk according to claim 1, characterized in that a half-adder-subtracter made up of 2 negating circuits and an OR circuit with 2 inputs and the following AND circuits: A not negated, B negated; A negates, B not negated; A not negated, B negated, i-line; A not negated, B not negated, s-line. (Type A). 3) Electronic parallel adding and subtracting unit according to claim 1, characterized in that a Haib adder-subtracter from 2 negating circuits and 2 OR circuits with 2 inputs each and the following AND circuits: A not negated, B negated; A negates, B not negated; B negated, i-line; 3 not negated, s-line. (Type B). 4) Electronic parallel adding and subtracting unit in hexadecimal dual code, characterized in that there are 4 switchable full adder-subtractors per "decade" having.