DE3030303A1 - Electronic adder operating in BCD-8421 code - has decimal display with number conversions by automatically adding binary code - Google Patents

Abstract

An electronic adding device operating in BCD-8421 Code and with a decimal display performs addition of a base number LHHL to a stored number LLLL before the first addition in each decade so that the stored values 15 and 6 corresp. to decimal 9 and 0 respectively. If the decade displays are set to zero an automatic additional addition of the same binary number LHHL is performed by doing carry additions. The adder decades each consist of five full and two half adders. There are eight storage flip-flops and a decoder in each adder decade. The necessary difference between the decade display and decade store values is automatically produced by adding the binary number LHHL. The difference between the carry input and output is balanced by addition of the correction number LHHL.

Description

Electronic adder in the BCD-842'13 # sa # l

with decimal display The invention relates to an adder in 3CD-8421 code in which in each adding decade before the first addition, automatically the basic number LHHL is added to the memory number B so that the adding decades are displayed is correct because the memory value 15 shows the decimal number 9 and the memory value 6 shows the digit zero. If in this way the decades displays of this adder are set to zero, is only automatic for carry additions Additional addition of the same binary number (LHHL) is required to make up the missing difference 16 - 10 = 6 = LHHL is balanced.

In Figure 1, the basic circuit of this adder, or

an adding decade is shown, which can only be used in conjunction with shift registers can be used. FIG. 2 simulates a decade of a special adder this basic principle, in which there is no shift register for entering subtotals is required because each total digit has a direct line in the relevant Input of the adding decade is entered. Also with this special adder In FIG. 2, the memory status of each decade must be converted to the binary number before the addition begins LHHL, because only real dual numbers are entered at the entrances. In Figure 3, the detail A of Figure 2 is shown.

The special adder, or a decade of this special adder According to Figure 2 consists of five full adders 1 and two half adders 2 and 8 memory flip-flopps 3 and a decoding circuit 4a The decades of this special adder have only one input row s because previous sums are via direct lines a come to input. Normal full adders are used as full adder 1 and half adder 2 and half adders for use. This adding decade has additional components six inner transmission lines b and 3 lines c and 3 lines d and a line e.

The correction line has the designation f and its branch the Designation h. The control lines are named i and k. The decade carry input has the designation 1 and the decade carry output the designation m 4 consists of 10 AND circuits 5 and four non-circuits (greed circuits) 6 and the associated cables. The line e and the lines d are made of transistors 7 driven and the lines n of transistors 8 (Figure 3). Have the entrances the designation A 1 to A 4. The additionally required control unit is not shown. The dual numbers that are added are sent via shift registers or directly fed to inputs 4 1 to A 4.

The mode of operation of an adding thedecade according to FIG. 2 results as follows follows: By automatically adding the basic number LHHL to inputs A 1 to A 4 the binary number LHHL is first added to the binary number LLLL (0), which results in the transistors 7 the potential rethe of the binary number LHHL is applied. Then the control unit takes over the control line i brought briefly to H potential and thus the potential series LHHL into the memory flip-flop series E entered. Then the control unit briefly sets the control line k to H potential brought and thus entered the potential series LHHL in the flip-flop series F.

In this way, the decoder circuit displays the decimal number zero.

Then the binary numbers that are to be added come on one after the other the inputs A 1 to A 4 brought into contact with the feedback input row the previous sum is always present and thus every sum supplied from a register Summand is added to the previous addition sum.

For the additions in which the memory value 15 is exceeded, the output m has H potential and will therefore be 1 for the next decade the number 1 is added.

Here, the sequence adders 2 a and 1 e also have on their left Input H potential and thus becomes the binary number present at inputs A 1 to A 4 plus correction number (LHHL) added to the previous total in one operation. The correction number is therefore the same as the basic number. The automatic additional addition the correction number is only required if a transfer to next decade.

A multi-digit decimal number to be added becomes each digit according to its decimal place of the associated decade in four digits dual coding supplied and thus stored for the binary number LLLL or the first Summands or for the first or a further partial sum of the corresponding decade added if the required by entering the basic number in each decade beforehand Initial state of the adder is established. The deletion of the in the flip flop series E and F dual numbers stored twice are carried out by simultaneous control the reset outputs of the flip-flopps with H-potential.

The addition of the basic number LHHL also takes place in all addition decades simultaneously.

If flip-flopps are more suitable, they should also be done at the line points p and q have resistors, such are used (FIG. 3). In figure 1 are the transistors 9 and in Figure 2 the transistors 7 and 8 as small black ones Semicircular areas shown. The arrangement of these transistors is shown in FIG.

The adder decade type B is shown in FIG.

In comparison to the adder decade type B (FIG. 1), the adder decade has Type A no control line v and no memory flip-flop row H.

Both Type A and Type B can also be equipped with a Decoding circuit 4 can be provided in accordance with FIG.

In the case of an adder with adding decades according to Figure 1 (Type B) the total is still displayed even if the two sumands are no longer are at the inputs of the adding decades.

The inputs of the adder decade type B (Figure 1) have the names A 1 to A 4 and B 1 to B 4 and the outputs are labeled D 1 to D 4.

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Claims (6)

Claims 0 Electronic adder in 3CD-8421 code, thereby characterized in that each adding decade consists of 5 full adders and 2 half adders. 2) Electronic adding unit according to claim 1, characterized in that that the memory value of the decades is higher than the display value by the binary number LHHL (6) of the decades. 3) Electronic adder according to claim 1 and 2, characterized in that that there is the required difference 6 between the decade display value and the decade storage value is generated by automatic addition of the binary number LHHL (6). 4) Electronic adding unit according to claim 1 to 3, characterized in that that the difference 6 between carry input and carry output by addition the correction number LHHL (6) is balanced. 5) Electronic adder according to claim 1 to 4, characterized in that that with a special type the adding decades are provided with two rows of Spelcher (E and F) are and that from the second memory row (F) direct lines to the corresponding Entrances are arranged. 6) Other electronic adders in the 8421 code, their decades display values are 6 lower than the decade memory values, characterized by that this required difference is produced by the fact that with each aggregate formation The number 6 (tRilt) is added once every decade.