DE3030490A1 - Electronic subtraction device with decimal display - performs conversion by automatically subtracting specified binary number - Google Patents

Abstract

The electronic subtraction device uses full-subtractors instead of full adders and half-subtractors instead of half adders. The necessary different of six in the values of the decade display value and the decade stored value is produced by inputting the minuend as a binary-plus-6 coded decimal number. The difference of six between the carry output and carry input in each decade is balanced by the automatic auxiliary subtraction of the correction number 6 or LHHL. In a special format, the subtraction decades have two rows (E,F) of stores. Direct connections (a) are made between the second row (F) of stores and the minuend inputs. Instead of performing auxiliary additions per decade, an additional decimal-binary coding circuit per decade may be used.

Description

Electronic subtracter in BCD-8421 code

with decimal display The invention relates to an electronic one Subtracter in BCD-8421 code with decimal display, in which compared to the ECD-8421 adder according to P 30 30 303.8 instead of 5 full adders and 2 half adders per decade 5 Full subtractors and 2 half subtractors are used. Even with this one Subtracter, the decade storage values are 6 (LHHL) higher than the Decade display values, because a decade transfer is only possible according to this principle is. Thus, a basic number 6 (LHHL) is also required, the addition of which at the end or at the end of the first minute is not possible, which is why this first At the end of each decade, a special ooding position is required, d e the relevant Brings decimal digit plus 6 dual coded to wingabe. This is possible because so that the upper limit of the storage value (15 = HHRH) is not exceeded and none The subtrahend digit to be entered is greater than the number 9 (HLLH).

In Figure 1, the subtracting decade type B is shown, which in multiple Arrangement forms a subtracter that is only used in conjunction with shift registers can be. FIG. 2 shows a decade of a special subtracter after this The basic principle is that there is no shift register for entering subsequent minuends is required because every minuend created by previous subtraction is entered into the associated input of the subtraction decade via a direct line will. FIG. 3 shows detail A from FIG. 2 and FIG. 4 shows a decimal-dual Godier circuit. Figure 5 shows the special Godier circuit.

The special subtracter consists of any number of decades according to FIG. 2. Each decade consists of 5 full subtractors VS and 2 half subtractors ES and 8 memory flip flopps 3 and a decoder circuit 4 and a special Coding circuit for the first minute end and a normal decimal-dual coding circuit. As a full subtracter VS and half-subtracters HS are normal types used here. As another This subtraction decade has components 5 inner carry lines b and 3 lines c and 3 lines d and one line e and 4 lines n. The core management has the designation f and its branch the designation h. The decade transfer input has the designation l and the decade carry output the designation n.

The decoding circuit 4 consists of 10 AND circuits 5 and 4 non-circuits 6 (negative circuits) and the associated lines. The line e and the lines d are controlled by transistors 7 and lines n by transistors 8 (FIG 3). The subtrahend ring lengths are named A 1 to A 4 and the minuend inputs the designation B 1 to B 4 for the first few days. The special Oodier circuit for entering the decimal digits of the first X digits is shown in FIG and a normal decimal-dual coding circuit for inputting a subtrahend decimal digit in Figure 4. For processing a minuend with 10 decimal places is a subtracter required, the minimum of 10 subtracting decades according to figure 2 exists. This also includes a circuit according to FIGS. 4 and 5. The controller takes place through an additionally required tail unit, which is not shown.

The mode of operation of a subtracter with subtracting decades according to FIG. 2 results as follows: First of all, everyone comes to inputs B 1 to B 4 Subtracting decade the corresponding dual-plus-6 coded decimal digit of the minute end to the system. Then the corresponding one comes at the inputs A 1 to A 4 of every decade Genuine dual-coded decimal digit of the subtrahend to the system, which means to the transistors 7 the potential series of the result number of this subtraction is present.

By means of an H-current pulse on the continuous control line i the potential series of these four-digit binary numbers are then transferred to the flip-flopp memory series E entered every decade. This is followed by the entry of these dual numbers into the flip-flopp memory rows F by means of an H current pulse at the also continuous Control line k, with which this subtraction result number on the one hand at the outputs of the decoding circuits 4 is displayed in decimal and on the other hand as a new minuend is again applied to the B inputs of the subtracting decades, because every subtracting decade Has 4 lines a. If the adjacent subtrahend has to be subtracted several times comes, the control lines i and k fed with an H-current pulse and thus the subtrahend n-fold from the minuend subtracted.

The current pulse of the line k must therefore be related to the current pulse the line i lag so far in time that the lines e and d on the one hand and the lines n, on the other hand, are not simultaneously conductive. Such a subtracter is therefore especially suitable for multiple subtraction in front of numbers, i.e. for executing g of divisions using the subtraction method, provided that the transistors are controlled 7 and 8 due to the different potentials of the lines d, e and n perfect is possible.

In the course of these subtractions, their stored value appears in the decades has fallen too far, at the outputs m a transfer of the size minus 16. As a result of the fact that this numerical value will not be full for the next few decades is deducted, but only the numerical value 10 in the form of minus 1 is in the Subtraction decades, which give off a carry, through the control lines f and h In addition, the binary number LHHL (6) is automatically subtracted (additional subtraction using the Flge subtracter).

Compared to the subtracting decade type B (Figure 1), the subtracting decade has Type A no control line v and no memory flip-flop row H. These too Both subtraction decades (Type A and Type B) are in a certain version with; a decoding circuit 4 according to Figure 2 and Oodierschaltuiigen according to Figure 4 and 5 provided.

The subtracting decade type B (Figure 1) also consists of 5 full subtractors VS and 2 half-subtractors HS and a flip-flop memory row H and a decoder circuit 4 corresponds to FIG. 2. The minuend inputs of this subtracting decade have the designation B 1 to B 4 and the subtrahend inputs are labeled A 1 to A 4. D 1 to D 4 are the outputs to which a decoding circuit is connected via corresponding branches 4 is connected according to FIG.

The special adder of the main patent application can be made as a special version be designed so that the basic number 6 does not have to be entered separately, but is entered with the first Sümmand. This is done by adding the first summand is entered by means of coding circuits according to FIG.

Version B of the special adder of the main patent application has not only feedback B inputs but also feedback B inputs in every decade and normal B inputs.

Claims (1)

Claims 1 electronic adder according to P 30 30 303.8 thereby characterized by using full subtractors instead of full Adders and by using Haib subtractors instead of half adders designed as electronic subtracters0 2) Electronic subtracters according to claim 1, characterized in that the required difference 6 between Decade display value and decade memory value by entering the end of the minute as dual-plus-6 coded Decimal digits is generated. 3) Electronic subtracters according to claim 1 and 2, characterized in that that in every decade the difference 6 between carry out (-16) and carry out (-10) compensated by automatic additional subtraction of the correction number 6 (LHHL) is 4) Electronic subtracters according to claim 1 to 3, characterized in that that with a special type the subtraction decades with two memory rows (E and F) are provided and there are direct lines (a) from the second memory row (F) the minuend inputs are arranged 0 5) Other electronic subtractors in 3421 code, whose decade display values are 6 lower than the decade memory values, characterized in that it thereby generates the required work difference that the input of the minuend or the first minuend in the form of dual-plus-6 coded Decimal digits SifOL 6) Electronic adding units according to P 30 30 303.8, characterized in that their special versions instead of the additional addition the basic number 6 (LHHL) an additional decimal-dual coding circuit per adding decade per decade, which produces dual-plus-6 encoded decimal digits, thus one Addend of each sum (total) in the form of dual-plus-6 coded decimal digits can be entered.