DE2800598A1 - Parallel-addierwerk - Google Patents

Parallel-addierwerk

Info

Publication number
DE2800598A1
DE2800598A1 DE19782800598 DE2800598A DE2800598A1 DE 2800598 A1 DE2800598 A1 DE 2800598A1 DE 19782800598 DE19782800598 DE 19782800598 DE 2800598 A DE2800598 A DE 2800598A DE 2800598 A1 DE2800598 A1 DE 2800598A1
Authority
DE
Germany
Prior art keywords
dec
digit
bit
carry
bits
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
DE19782800598
Other languages
German (de)
English (en)
Inventor
Samuel Robert Levine
Shanker Singh
Arnold Weinberger
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of DE2800598A1 publication Critical patent/DE2800598A1/de
Withdrawn legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/491Computations with decimal numbers radix 12 or 20.
    • G06F7/492Computations with decimal numbers radix 12 or 20. using a binary weighted representation within each denomination
    • G06F7/493Computations with decimal numbers radix 12 or 20. using a binary weighted representation within each denomination the representation being the natural binary coded representation, i.e. 8421-code
    • G06F7/494Adding; Subtracting
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50Adding; Subtracting
    • G06F7/505Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/506Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages
    • G06F7/508Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages using carry look-ahead circuits
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/3804Details
    • G06F2207/3808Details concerning the type of numbers or the way they are handled
    • G06F2207/3832Less usual number representations
    • G06F2207/3844Hexadecimal
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/492Indexing scheme relating to groups G06F7/492 - G06F7/496
    • G06F2207/4921Single digit adding or subtracting

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)
  • Complex Calculations (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
DE19782800598 1977-01-10 1978-01-07 Parallel-addierwerk Withdrawn DE2800598A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/758,378 US4118786A (en) 1977-01-10 1977-01-10 Integrated binary-BCD look-ahead adder

Publications (1)

Publication Number Publication Date
DE2800598A1 true DE2800598A1 (de) 1978-07-13

Family

ID=25051516

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19782800598 Withdrawn DE2800598A1 (de) 1977-01-10 1978-01-07 Parallel-addierwerk

Country Status (6)

Country Link
US (1) US4118786A (US06420036-20020716-C00037.png)
JP (1) JPS5387638A (US06420036-20020716-C00037.png)
DE (1) DE2800598A1 (US06420036-20020716-C00037.png)
FR (1) FR2377063A1 (US06420036-20020716-C00037.png)
GB (1) GB1593336A (US06420036-20020716-C00037.png)
IT (1) IT1114185B (US06420036-20020716-C00037.png)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IL59907A0 (en) * 1980-04-23 1980-06-30 Nathan Grundland Arithmetic logic unit
US4866656A (en) * 1986-12-05 1989-09-12 American Telephone And Telegraph Company, At&T Bell Laboratories High-speed binary and decimal arithmetic logic unit
JPH01115340A (ja) * 1987-10-29 1989-05-08 Nagashima Ika Kikai Kk 総合視運動検査装置
JPH01115341A (ja) * 1987-10-29 1989-05-08 Nagashima Ika Kikai Kk 総合視運動検査装置におけるプロジェクタ
US7325025B2 (en) * 2001-12-18 2008-01-29 Intel Corporation Look-ahead carry adder circuit
US7299254B2 (en) * 2003-11-24 2007-11-20 International Business Machines Corporation Binary coded decimal addition
US7546328B2 (en) * 2004-08-31 2009-06-09 Wisconsin Alumni Research Foundation Decimal floating-point adder
US7743084B2 (en) * 2004-09-23 2010-06-22 Wisconsin Alumni Research Foundation Processing unit having multioperand decimal addition

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3596074A (en) * 1969-06-12 1971-07-27 Ibm Serial by character multifunctional modular unit
US3629565A (en) * 1970-02-13 1971-12-21 Ibm Improved decimal adder for directly implementing bcd addition utilizing logic circuitry
US3711693A (en) * 1971-06-30 1973-01-16 Honeywell Inf Systems Modular bcd and binary arithmetic and logical system
US3752394A (en) * 1972-07-31 1973-08-14 Ibm Modular arithmetic and logic unit
US3958112A (en) * 1975-05-09 1976-05-18 Honeywell Information Systems, Inc. Current mode binary/bcd arithmetic array
JPS5384647A (en) * 1976-12-30 1978-07-26 Fujitsu Ltd High-speed adder for binary and decimal

Also Published As

Publication number Publication date
JPS5628303B2 (US06420036-20020716-C00037.png) 1981-07-01
IT1114185B (it) 1986-01-27
FR2377063A1 (fr) 1978-08-04
JPS5387638A (en) 1978-08-02
FR2377063B1 (US06420036-20020716-C00037.png) 1980-01-04
GB1593336A (en) 1981-07-15
US4118786A (en) 1978-10-03

Similar Documents

Publication Publication Date Title
DE3854321T2 (de) Populationszählung in Rechnersystemen.
DE1956209C3 (de) Multipliziervorrichtung
DE3686681T2 (de) Parallelmultiplizierer.
DE69731700T2 (de) Arithmetischer Schaltkreis und arithmetisches Verfahren
DE3607045A1 (de) Digitale addier- und subtrahierschaltung
DE2018452A1 (de) Arithmetische Einrichtung
DE2626432A1 (de) Arithmetische einheit fuer automatische rechengeraete
DE4101004C2 (de) Paralleler Multiplizierer mit Sprungfeld und modifiziertem Wallac-Baum
DE69434806T2 (de) Verfahren, System und Vorrichtung zum automatischen Entwurf einer Multiplikatorschaltung und durch die Durchführung dieses Verfahrens entworfene Multiplikatorschaltung
DE2758130C2 (de) Binärer und dezimaler Hochgeschwindigkeitsaddierer
DE2352686B2 (de) Dezimaler Parallel-Addierer/Substrahierer
EP0383965A1 (de) Multiplizierwerk
DE1549508C3 (de) Anordnung zur Übertragsberechnung mit kurzer Signallaufzeit
DE2800598A1 (de) Parallel-addierwerk
DE2826773A1 (de) Verfahren und schaltungsanordnung zum feststellen der wertigkeit von ziffern in arithmetischen operationen mit dezimalrechnern
DE3434777C2 (US06420036-20020716-C00037.png)
EP0257362A1 (de) Addierer
DE3610875A1 (de) Subtrahierer in komplementaerer metalloxid-halbleitertechnologie
EP0130397B1 (de) Digitales Rechenwerk
DE3326388C2 (US06420036-20020716-C00037.png)
DE68928370T2 (de) Logikschaltung mit Uebertragungsgesteuerten Addierer
DE2727051B2 (de) Einrichtung zur binären Multiplikation einer ersten Zahl als Multiplikand mit einer den Multiplikator ergebenden Summe aus einer zweiten und dritten Zahl im Binärcode
DE4317074C1 (de) Multiplizierer für reelle und komplexe Zahlen
EP0752130B1 (de) Multiplizierer mit geringer laufzeit
DE3854284T2 (de) Paralleladdierer mit entfernten Abhängigkeiten.

Legal Events

Date Code Title Description
8139 Disposal/non-payment of the annual fee