DE3686681T2 - Parallelmultiplizierer. - Google Patents

Parallelmultiplizierer.

Info

Publication number
DE3686681T2
DE3686681T2 DE8686110067T DE3686681T DE3686681T2 DE 3686681 T2 DE3686681 T2 DE 3686681T2 DE 8686110067 T DE8686110067 T DE 8686110067T DE 3686681 T DE3686681 T DE 3686681T DE 3686681 T2 DE3686681 T2 DE 3686681T2
Authority
DE
Germany
Prior art keywords
parallel multiplier
multiplier
parallel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE8686110067T
Other languages
English (en)
Other versions
DE3686681D1 (de
Inventor
Shigeru Tanaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of DE3686681D1 publication Critical patent/DE3686681D1/de
Publication of DE3686681T2 publication Critical patent/DE3686681T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • G06F7/53—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel
    • G06F7/5306—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel with row wise addition of partial products
    • G06F7/5312—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel with row wise addition of partial products using carry save adders

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Complex Calculations (AREA)
DE8686110067T 1985-07-23 1986-07-22 Parallelmultiplizierer. Expired - Lifetime DE3686681T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60162541A JPS6222146A (ja) 1985-07-23 1985-07-23 並列乗算器

Publications (2)

Publication Number Publication Date
DE3686681D1 DE3686681D1 (de) 1992-10-15
DE3686681T2 true DE3686681T2 (de) 1993-02-04

Family

ID=15756565

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8686110067T Expired - Lifetime DE3686681T2 (de) 1985-07-23 1986-07-22 Parallelmultiplizierer.

Country Status (4)

Country Link
US (1) US4791601A (de)
EP (1) EP0210579B1 (de)
JP (1) JPS6222146A (de)
DE (1) DE3686681T2 (de)

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5153847A (en) * 1986-06-27 1992-10-06 Matsushita Electric Industrial Co., Ltd. Arithmetic processor using signed digit representation of internal operands
JPH07111678B2 (ja) * 1987-05-29 1995-11-29 松下電器産業株式会社 加算装置
US5206825A (en) * 1987-05-27 1993-04-27 Matsushita Electric Industrial Co., Ltd. Arithmetic processor using signed-digit representation of external operands
JPS6453228A (en) * 1987-08-24 1989-03-01 Mitsubishi Electric Corp Logic circuit for multiplier
KR920003908B1 (ko) * 1987-11-19 1992-05-18 미쓰비시뎅끼 가부시끼가이샤 승산기(乘算器)
JPH07120272B2 (ja) * 1988-04-12 1995-12-20 日本電気株式会社 算術演算回路
JPH0776914B2 (ja) * 1988-10-18 1995-08-16 三菱電機株式会社 乗算回路
US5038315A (en) * 1989-05-15 1991-08-06 At&T Bell Laboratories Multiplier circuit
US5262976A (en) * 1989-11-13 1993-11-16 Harris Corporation Plural-bit recoding multiplier
US5412591A (en) * 1990-08-09 1995-05-02 Vlsi Technology, Inc. Schematic compiler for a multi-format high speed multiplier
US5291431A (en) * 1991-06-03 1994-03-01 General Electric Company Array multiplier adapted for tiled layout by silicon compiler
US5251167A (en) * 1991-11-15 1993-10-05 Amdahl Corporation Method and apparatus for processing sign-extension bits generated by modified booth algorithm
US5361220A (en) * 1991-11-29 1994-11-01 Fuji Photo Film Co., Ltd. Discrete cosine transformation with reduced components
US5477479A (en) * 1993-03-08 1995-12-19 Nkk Corporation Multiplying system having multi-stages for processing a digital signal based on the Booth's algorithm
US5576765A (en) * 1994-03-17 1996-11-19 International Business Machines, Corporation Video decoder
KR960042334A (ko) * 1995-05-15 1996-12-21 김주용 병렬 독립 다중비트 가산기
JP3351672B2 (ja) * 1995-12-20 2002-12-03 株式会社東芝 加算器
JPH09269891A (ja) * 1996-04-01 1997-10-14 Hitachi Ltd 部分積加算方法および装置、浮動小数点乗算方法および装置、浮動小数点積和演算方法および装置
US6183122B1 (en) * 1997-09-04 2001-02-06 Cirrus Logic, Inc. Multiplier sign extension
US6687722B1 (en) * 2000-03-16 2004-02-03 Agere Systems, Inc. High-speed/low power finite impulse response filter
GB0317570D0 (en) * 2003-07-26 2003-08-27 Koninkl Philips Electronics Nv Long-integer multiplier
JP4170267B2 (ja) * 2004-07-09 2008-10-22 Ｎｅｃエレクトロニクス株式会社 乗算剰余演算器及び情報処理装置
JP4180024B2 (ja) * 2004-07-09 2008-11-12 Ｎｅｃエレクトロニクス株式会社 乗算剰余演算器及び情報処理装置
US7424507B1 (en) * 2004-09-30 2008-09-09 National Semiconductor Corporation High speed, low power, pipelined zero crossing detector that utilizes carry save adders
US10831445B1 (en) 2018-09-20 2020-11-10 Groq, Inc. Multimodal digital multiplication circuits and methods

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4153938A (en) * 1977-08-18 1979-05-08 Monolithic Memories Inc. High speed combinatorial digital multiplier
JPS5663649A (en) * 1979-10-26 1981-05-30 Nec Corp Parallel multiplication apparatus
US4484301A (en) * 1981-03-10 1984-11-20 Sperry Corporation Array multiplier operating in one's complement format
US4646257A (en) * 1983-10-03 1987-02-24 Texas Instruments Incorporated Digital multiplication circuit for use in a microprocessor
US4575812A (en) * 1984-05-31 1986-03-11 Motorola, Inc. X×Y Bit array multiplier/accumulator circuit

Also Published As

Publication number Publication date
JPS6222146A (ja) 1987-01-30
DE3686681D1 (de) 1992-10-15
EP0210579A2 (de) 1987-02-04
EP0210579B1 (de) 1992-09-09
EP0210579A3 (en) 1990-01-10
US4791601A (en) 1988-12-13
JPH0456339B2 (de) 1992-09-08

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Legal Events

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8364 No opposition during term of opposition
8320 Willingness to grant licences declared (paragraph 23)