DE2629996A1 - Verfahren zur passivierung und planarisierung eines metallisierungsmusters - Google Patents

Verfahren zur passivierung und planarisierung eines metallisierungsmusters

Info

Publication number
DE2629996A1
DE2629996A1 DE19762629996 DE2629996A DE2629996A1 DE 2629996 A1 DE2629996 A1 DE 2629996A1 DE 19762629996 DE19762629996 DE 19762629996 DE 2629996 A DE2629996 A DE 2629996A DE 2629996 A1 DE2629996 A1 DE 2629996A1
Authority
DE
Germany
Prior art keywords
layer
metallization pattern
metallization
photoresist
quartz
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
DE19762629996
Other languages
German (de)
English (en)
Inventor
Gabor Dr Paal
Klaus Dr Schackert
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
IBM Deutschland GmbH
Original Assignee
IBM Deutschland GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by IBM Deutschland GmbH filed Critical IBM Deutschland GmbH
Priority to DE19762629996 priority Critical patent/DE2629996A1/de
Priority to FR7717620A priority patent/FR2357070A1/fr
Priority to US05/807,693 priority patent/US4089766A/en
Priority to GB26166/77A priority patent/GB1521950A/en
Priority to JP7564777A priority patent/JPS536588A/ja
Publication of DE2629996A1 publication Critical patent/DE2629996A1/de
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02118—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Thin Film Transistor (AREA)
  • Manufacturing Of Printed Circuit Boards (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Formation Of Insulating Films (AREA)
  • Weting (AREA)
DE19762629996 1976-07-03 1976-07-03 Verfahren zur passivierung und planarisierung eines metallisierungsmusters Withdrawn DE2629996A1 (de)

Priority Applications (5)

Application Number Priority Date Filing Date Title
DE19762629996 DE2629996A1 (de) 1976-07-03 1976-07-03 Verfahren zur passivierung und planarisierung eines metallisierungsmusters
FR7717620A FR2357070A1 (fr) 1976-07-03 1977-06-03 Procede permettant de passiver et de rendre planaire une configuration metallique
US05/807,693 US4089766A (en) 1976-07-03 1977-06-17 Method of passivating and planarizing a metallization pattern
GB26166/77A GB1521950A (en) 1976-07-03 1977-06-22 Method of insulating a metallization pattern
JP7564777A JPS536588A (en) 1976-07-03 1977-06-27 Method of inactivating and flattening metallic pattern

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19762629996 DE2629996A1 (de) 1976-07-03 1976-07-03 Verfahren zur passivierung und planarisierung eines metallisierungsmusters

Publications (1)

Publication Number Publication Date
DE2629996A1 true DE2629996A1 (de) 1978-01-05

Family

ID=5982138

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19762629996 Withdrawn DE2629996A1 (de) 1976-07-03 1976-07-03 Verfahren zur passivierung und planarisierung eines metallisierungsmusters

Country Status (5)

Country Link
US (1) US4089766A (enExample)
JP (1) JPS536588A (enExample)
DE (1) DE2629996A1 (enExample)
FR (1) FR2357070A1 (enExample)
GB (1) GB1521950A (enExample)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0012863A3 (en) * 1978-12-26 1980-10-15 International Business Machines Corporation Method of making semiconductor devices with reduced parasitic capacitance
DE19720974C1 (de) * 1997-05-20 1998-07-02 Deutsche Spezialglas Ag Vorsatzfilter für selbstleuchtende Bildschirme

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4176029A (en) * 1978-03-02 1979-11-27 Sperry Rand Corporation Subminiature bore and conductor formation
US4263603A (en) * 1978-03-02 1981-04-21 Sperry Corporation Subminiature bore and conductor formation
US4244799A (en) * 1978-09-11 1981-01-13 Bell Telephone Laboratories, Incorporated Fabrication of integrated circuits utilizing thick high-resolution patterns
US4564575A (en) * 1984-01-30 1986-01-14 International Business Machines Corporation Tailoring of novolak and diazoquinone positive resists by acylation of novolak
US4481070A (en) * 1984-04-04 1984-11-06 Advanced Micro Devices, Inc. Double planarization process for multilayer metallization of integrated circuit structures
US4541169A (en) * 1984-10-29 1985-09-17 International Business Machines Corporation Method for making studs for interconnecting metallization layers at different levels in a semiconductor chip
US4654120A (en) * 1985-10-31 1987-03-31 International Business Machines Corporation Method of making a planar trench semiconductor structure
US4721689A (en) * 1986-08-28 1988-01-26 International Business Machines Corporation Method for simultaneously forming an interconnection level and via studs
US6147393A (en) * 1993-05-05 2000-11-14 Ixys Corporation Isolated multi-chip devices
US6107674A (en) * 1993-05-05 2000-08-22 Ixys Corporation Isolated multi-chip devices

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2547792C3 (de) * 1974-10-25 1978-08-31 Hitachi, Ltd., Tokio Verfahren zur Herstellung eines Halbleiterbauelementes

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0012863A3 (en) * 1978-12-26 1980-10-15 International Business Machines Corporation Method of making semiconductor devices with reduced parasitic capacitance
DE19720974C1 (de) * 1997-05-20 1998-07-02 Deutsche Spezialglas Ag Vorsatzfilter für selbstleuchtende Bildschirme

Also Published As

Publication number Publication date
FR2357070B1 (enExample) 1980-02-08
FR2357070A1 (fr) 1978-01-27
US4089766A (en) 1978-05-16
JPS536588A (en) 1978-01-21
GB1521950A (en) 1978-08-23

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Legal Events

Date Code Title Description
8139 Disposal/non-payment of the annual fee