DE2525097A1 - Field effect transistor for memory applications - uses supplementary gate from which store state is read out - Google Patents

Abstract

'N' channel field effect transistor intended for use in telephone switching systems and data processing equipment, has a floating memory gate or grid isolated by some dielectric material and is negatively charged by the input program by electron injection. A second gate is charged positively with respect to the 'N' channel when reading out the memory state of the transistor, such that the drain-source circuit is conducting during its non-programmed state and conducting in its programmed state. The channel length is less than 10 microns, normally 1 to 3 microns and the substrate resistivity 3 to 10 ohms/cm.

Description

n-channel memory FET The invention represents a particular embodiment one in the Faupt application / main patent P 25 05 816.6 = 75 P 6016 BRD of the treated Subject matter - this main application / main patent is itself an addition for application / patent P 24 45 137.4 = 74/6185.

The invention relates to a special development in the main application / main patent detected erasure method of an electronic manufactured in integrated technology Component with memory properties, which is for use in a program memory a telephone switching system was developed, but which also for others Memory, e.g. B. for program memory of data processing systems is suitable.

In the aforementioned application / patent P 24 45 137.4 is an n-channel memory FET with a controllable control gate having a connection, compare there Fig. 1, and with a floating memory gate surrounded on all sides by an insulator described, with its memory gate being programmed by means of channel injection generated, heated electrons is negatively charged and with its storage gate after this charge, especially when reading, by means of its negative charge Influence in the drain-source current in an inhibiting manner on the drain-source path acts. An example is also shown there, compare FIG. 4 and page 10, line 1 and 2 as well as the local ones current claim 16, wherein such an n-channel memory FET multiple in a memory matrix, in integrated Technique made on a substrate, is provided, each n-channel memory FET each forms a memory cell for itself. Here are the connections of the control gates one memory line each via a first control line X, and one of the connections of the two main lines of all memory FETs with one another Conductively connected via a common connection point So.

According to the main application / main patent P 25 OS 816.0, page 1, paragraph 1 and the current claim 1 there, the loaded, i.e. programmed Memory gate of such memory cells with the help of electrical means, namely by means of an erase voltage applied between the control gate and the main line, be discharged by an effect of the electrons stored in the storage gate, caused by the erase voltage in the direction away from the memory gate into the insulator between Storage gate and main line are accelerated into it, to drain through the Insulator to the main line, i.e. to the channel or to the drain or to the source, caused. For this purpose, an erase voltage of the appropriate polarity and amplitude is applied between the control gate and that area of the main line where the unloading is to take place. In the present invention, said effect is mainly due to the Fowler-Nordheim tunnel effect formed, which was already described in the main application / main patent. there was already disclosed on page 22, last paragraph, that the electron discharge current, that flows from the memory gate to the main line is often a hole discharge current superimposed, which because of its opposite current direction also the memory gate discharges.

The parent application / patent also reveals that the n-channel memory FET both with the help of the Fowler-Nordheim tunnel effect, i.e. with electrical means, Repeatedly electrically erased, as well as subsequently electrically new can be programmed. The electrical erasure and also the electrical reprogramming can, with suitable voltage amplitudes, advantageously within a short time, namely z.3. within a few 10 ms, e.g. with approx. 35 V voltage pulses between Storage gate and main line, when deleting for the first time and e.g. within a Minute at the 20th deletion. The measured deletion times change so normally, and indeed they increase from deletion to deletion. The duration of the deletion will eventually exceed a maximum permissible value that can be determined at will, from which one can consider the deletion as disturbed and no longer possible. The effort required for electrical extinguishing is low. Using a n-channel instead of p-channel for the memory FET is necessary, otherwise none Programming using channel injection and subsequent deletion using the Fowler-Nordheini tunnel effect is possible.

The invention is based on new knowledge about the causes and about the remedial possibilities of the growing from programming to programming, Required deletion times in each case. The invention solves the problem of the increase in the deletion times, that can otherwise be observed from deletion to deletion, must be greatly reduced. Since the the erasing times required by the invention grow considerably more slowly - if they grow at all - with the help of the measure according to the invention, the number which considerably increases the number of deletions and reprogramming that are possible without interference will.

The invention also extends the life of the memory FET increased because the deletion times no longer reach impermissibly high values as quickly.

The invention thus relates to an n-channel memory FET with a one Connection having controllable control gate and with an isolator on all sides surrounded, floating memory gate, whereby its memory gate during programming by Negative heated electrons generated by channel injection in one's own channel is charged, with its storage gate after this charging, especially when reading, inhibiting the drain-source current by virtue of its negative charge due to influence in the drain-source current Acts on the drain-source path, i.e. the main path, whereby the charged, So programmed memory gate with electrical means, namely by means of a between the control gate and the main line supplied erase voltage by the Fowler-Nordheim tunnel effect is discharged, the electrons stored in the storage gate, caused by the erase voltage in the direction away from the memory gate into the insulator between Storage gate and main line are accelerated into it, to drain through the Insulator to the main line, i.e. to the channel or to the drain or to the source, causes and for this purpose the erase voltage of the corresponding polarity between the control gate and that area of the main line is created where the discharge is to take place. The inventive n-channel memory FET is characterized in that when erasing the erase voltage applied between the control gate and the main line, slowly, e.g. within a few seconds, increases to its final value. The erase voltage It can be, for example, in a sawtooth shape, or in a pulse shape with a very flat rise Leading edge and constant, the roof corresponding to the final value 'or through an amplitude-modulated pulse sequence with slowly increasing *) The achieved thereby Improvements in deletion, i.e. greater freedom from interference, and further training of the invention are based on the embodiments shown in FIGS explained in more detail, the *) amplitude being formed.

1 shows memory FETs according to the invention arranged in a memory matrix and FIG. 2 shows a particular embodiment of a single memory FET.

In Fig. 1, n-channel memory FETs T1 to T4 are shown. The two-dimensional The memory array can also contain many more than just four such memory FETs. The individual memory FETs each contain a controllable control gate one surrounded on all sides by an insulator and floating in electrical terms Memory gate, compare e.g. in Fig. 2 the memory gate G1. The storage gate will when programming with electrons, here Ke, which are injected into their own channels Channel, here at channel point Y, generated, i.e. heated, negatively charged. After this negative charge, the storage gate, here G1, works especially with the Reading, by means of its negative charge due to influence in the drain-source current inhibiting way on the main line, here on its first part K1. After this Programming is therefore the main route, here K1 / K2, in an overly blocking one State controlled, as detailed in the above-cited application / patent P 24 45 137.4-53 is described.

The loaded, that is programmed, memory gate, here G1, can according to the main application / main patent with electrical means, namely by means of a between the control gate and the main line supplied erase voltage by the Fowler-Nordheim tunnel effect. the irrrim storage gate stored Causes electrons to flow away through the insulator, here Is, to the main route. In the main application main patent is also described that when deleting this Electron discharge current a hole discharge current at the same point of the May overlay the isolator.

The holes tile in the opposite direction as the Electrons, so that the hole discharge current also discharges onto the memory gate G1 works.

The invention is based on the knowledge that the hole discharge current essentially due to the avalanche effect superimposed on the Fowler-Nordheim tunnel effect arises. This avalanche effect is particularly evident in the main application / main patent in connection with the curve F2 of FIG. 2 there. It was found, that the strong increase in the duration of the deletion from deletion to deletion, especially with the Occurrence of the hole discharge current is related. Because of the holes will be namely the traps that are normally unavoidable in the isolator Is filled with holes which poison the insulator. This in the isolator Adhering holes cause an increase in the minimum erasing voltages necessary for the erasure and the deletion times required for deletion.

It turned out that the sharp increase in the extinguishing times, which otherwise leads to total poisoning and total disturbance of the extinctions, completely or at least can at least largely be avoided if the erasing voltage is used when erasing - compare Ur / Ut in Fig. 1, what is between the control gate G2 and the main line here the storage FET T3 is applied ~ - only slowly rise to its final value leaves. The erasing voltage should, for example, be continuous within a sawtooth shape of three seconds from zero V to its final value, e.g. + 35 V, between the main line and the control gate G2 rise. For this purpose, one can use constant Erdsotentinl for the potential Ut and choose a positive, increasing potential for the potential Ur. Man can also use a corresponding amplitude-modulated sequence of positive pulses for erasing use, the amplitude of which is just as slowly sawtooth-shaped, as it were continuously, increases - in this case it is an amplitude-modulated pulse train, the envelope curve of the amplitude peak slowly and continuously in a sawtooth shape the final value at which the memory gate is deleted increases. The final value of the Sawtooth voltage can then constant for some time continue in order to continue the discharge during this time.

By such a slowly increasing erase voltage, instead of one of At the beginning of a high erase voltage, the storage gate G1 only discharges slowly little by little, as soon as the voltage Fl between the memory gate and the main line, that is Drain or source is reached. Due to the now beginning discharge of the storage gate this tension has a tendency to decrease. But because the control gate mainline erase saving continues to rise, the voltage between the memory gate and the main line is nonetheless furthermore equal to the minimum possible voltage for the Fowler-Ncrdheim tunnel effect F1 or only slightly higher, compare F1 in Fig. 2 of the main application / main patent-especially with optimal dimensioning of the insulator thickness x. The discharge takes place at the Invention only through the Fowler-Nordheim tunnel effect because between the memory gate Gl and the main line effective in spite of the slow control gate main line voltage rise Due to the smallness of the electrical discharge current, the voltage remains approximately constant is in each case smaller than F2, so that none is superimposed due to the avalanche effect Hole discharge current can flow simultaneously - compare those for generation of a hole discharge current necessary, high, not reached in the invention Minimum tension F2 in Fig. 2 of the main application / main patent, as long as the thickness x of the isolator Is not unusually large values, compare 11002 in FIG. 2 of FIG Main application / main patent, exceeds. Due to the measure according to the invention the hole discharge current superimposed by the avalanche effect is thus avoided. Instead, the erase voltage increases slowly according to the invention only the Fowler-Nordheim-Ttinnel effect, which is advantageous for relatively low voltages gradually causes the discharge of the memory gate G1.

Since the invention avoids the hole discharge current, are the traps in the isolator Is no longer occupied by such holes. During the slow rise of the control gate main-path erase voltage flows in the invention gradually, so only gradually, the electron discharge current, without the The voltage between the memory gate G1 and the main line corresponds to that of curve 2 Height reached. The increase in the erase voltage Ur / Ut should therefore be so in the case of the invention take place slowly so that no hole discharge current flows and that the erase time remains as constant as possible - an indication of the flow of punch discharge current is obtained by measuring the voltage between the floating substrate HT and that Area S or D towards which the electron discharge is to take place; this tension increases if there are also holes flowing. The highest permissible value for the invention for the rapidity of the increase in the erase voltage can be chosen for the particular Structure of the memory FET also determined by an experiment on a sample Only such a rapidity of this increase is permissible, in spite of repeated deletion and reprogramming no longer significantly increases the respective Duration of extinction is observed.

Because of this avoidance of the poisoning can now also the deletion Be approved via the same isolator point that was used for programming. You can therefore, compare FIG. 2, the programming at a drain near the first Channel point V cause by means of the heated electrons Ke and then dle Erasure to the drain D by means of the electron discharge current Kd over practically cause the same isolator point. In this case, too, one does not observe that otherwise usual, uncomfortably strong increase in the deletion time and the reprogramming time and also not the insufficient charging of the storage gate, which is common in the case of poisoning after reprogramming.

In order to improve the erasure of the memory FET according to the invention, a further development can be used which prevents excessive discharge of the memory gate G1 allows without the entire channel of the storage FET due to this excessive discharge is controlled in the conductive state. In this training it is intended that the memory gate of the memory FET is only one across the entire width of the channel extending first part, compare K1 in Fig. 2 of the channel K1 / K2 covered. This first channel part Kl should contain the few channel point V, which by means of Channel injection emits heated electrons when programming; - or the first channel part K1 should at least adjoin this channel point V. Additionally it is provided that a control gate G2, but not the memory gate G1, in each case remaining, electrically in series part, compare K2 in Fig. 2, of the channel covered so that the state of the first part K1 of the channel both from the control gate state as well as the memory gate state, but the state of the remaining part K2 of the Channel is only controlled by the control gate state. Such a structure of the memory FET is already described in the application / patent P 25 13 207.4 = 75 P 6039.

FIG. 1 shows a memory array similar to that shown in FIG. 4 of the application / patent P 24 45 137.4 corresponds approximately to the memory matrix shown. The here in Fig. 1 The memory matrix shown is, however, with the embodiments of the shown in FIG Storage FET equipped. Storage matrices with such developments can advantageously can be operated differently when deleting: First, the bit-wise can be used in a single Information stored in the memory FET can be deleted. To do this, the extinguishing voltage, e.g. to delete the memory FET T3, between the associated control electrode, here X2 and the corresponding drain, i.e. Y1, are effective. One can use as ¢ e.g. the ascending Extinguishing voltage by applying the potentials Us1 = 0V ... + 35V and Ut1 = OV to the selected memory cell, here under control of switch T5 in the conductive state. In this case, the isolated, floating memory gate of the memory cell T3 stored negative charge via the Drain D of this memory cell to switch T5. To the rest with the control gates connected control lines X can each e.g. + 20V, to the others with the Drains connected to the control lines Y are each 0 V and the common Switching point So can float to avoid unwanted influences i.e. deletions and programming to avoid the unselected memory cells T1, T2, T4. By floating the common circuit point So one avoids at the same time the flow of main line currents that generate unnecessary heat loss.

Secondly, those stored in a line of memory can also be used word by word Total information, or the total information stored in several such lines can be electrically deleted at the same time. In addition, the relevant potentials are all correspondingly assigned matrix control lines X, Y to be supplied. That way the entire information stored in all lines can also be electrical at the same time are deleted by adding the relevant potentials to all matrix control lines When programming a memory cell, e.g. T3, a programming potential Ut2 with e.g. + 20V to the memory cell assigned to this memory cell with the control gate G2 connected control line, here X2. The programming potential Ut2 accelerates the free electrons heated by the channel injection in the channel to the memory gate G1, as in the above-mentioned applications / patents is described in detail. So that the channel point in question V by channel injection the free electrons Ke emitted, which charge the memory gate G1, is the main route of the concerned Memory FET, here T3, a programming voltage, v # L.

Ur2 / Us2 e.g. with the potentials Ur2 = OV, Us2 = + 20V. By supplying the potential OV to the remaining matrix control lines X1, Y2 the remaining memory FETs T1, T2, T4 not programmed, not read and not deleted - these remaining memory FETs then also consume no current, so no energy.

The memory shown in Fig. 1 can be without significant constructive Effort can also be read. When reading a selected memory cell, e.g. T3, such a reading potential Ut3, e.g. + 5V, can be applied to the control line connected to the control gate, here X2, which the Controls the main line of the relevant storage cell, here T5, to the conductive state, if the memory cell T3 is not programmed, and which is the main line, here namely the first channel part K1 of the memory cell structure shown in FIG. 2, does not control into the conductive state, whereby T3 remains blocked if the memory cell T3 is programmed. Whether the main line of the memory cell in question is conductive or blocking, is activated by a simultaneous supply of a reading voltage, here Ur3 / Us3, determined via switch T5 belonging to the relevant column, E.g. with Ur3 = + 5 V and Us3 = O V. When reading a memory cell, here a read potential of the control line assigned to the control gate of this memory cell X2, and additionally a read voltage Ur3 / Us3 of the main line of this memory cell fed. The current flowing through the main section K1 / K2 forms a signal that controls the output amplifier LV. This output amplifier monitors whether a Current flows or not, that is, whether the memory cell T3 programs or not programmed.

When reading, as well as e.g. OV can be created during programming, see Fig. 1.

This ensures that none of the unselected memory FETs a current can flow.

4 claims a figures

Claims (4)

Claims cì n-channel memory FET with one port having controllable control gate and with an insulator on all sides surrounded, floating memory gate, with its memory gate when programming negative by heated electrons generated in one's own channel by means of channel injection is charged, with its storage gate after this charging, especially when reading, inhibiting drain-source current by means of its negative charge due to influx in the drain-source current Acts on the drain-source path, i.e. the main path, whereby the charged, So programmed memory gate with electrical means, namely by means of a between the control gate and the main line supplied erase voltage by the Foarius-Nordheim tunnel effect is discharged, the electrons stored in the storage gate, caused by the erase voltage in the direction away from the memory gate into the insulator between Storage gate and main line are accelerated into it, to drain through the Insulator to the main line, i.e. to the channel or to the drain or to the source, causes and for this purpose the cancellation voltage of the corresponding polarity between the control gate and that area of the main line is placed where the unloading is to take place, according to application patent P 25 05 816.6 = 75 P 6016 BRD especially for program memory of a telephone switching system that is not indicated that when erasing the erase voltage # Us1 / Ut1, sawtooth voltage) that is between the Control gate (G2) and the main line (D) is applied, slowly (3 seconds) on its final value (+ 35V) increases. 2. n-channel memory FET according to claim 1, d a d u r c h g e -k e n It is noted that a memory gate (G1) only extends over the whole Width of the channel (K1 / K2) extending first part (K1) of the channel covered, which contains that channel point (V), which by means of channel injection when Programming the heated electrons (Ke) emitted or at least to these Channel location (V) adjoins, and that its control gate (G2), but not its memory gate (G1) covers the remaining, electrically in series part (K2) of the duct, so that the state of the first part (K1) of the channel depends on both the memory gate state as well as the control gate state, but the state of the remaining part (K2) of the Channel is only controlled by the control gate state. 3. n-channel memory FET according to claim 1 or 2, d a d u r c h g e it is not noted that the memory gate (G1) is close to that isolator location (v) is discharged (Kd), via which the programming (Ke) takes place. 4. n-channel memory FET according to one of the preceding claims, d a d u r c h g e k e n n n z e i n e t that to prevent the deletion of a programmed memory FET (T1), on whose main line (D) a to delete a other storage FETs (T3) connected to it, an erasure potential (OV .... + 35V) is applied - at the same time to the control gate (G2) of this memory FET (TI) a defined potential (+ 20V) that avoids erasure is supplied.