DE2808072A1 - N-channel storage FET for telephone exchange system - has thickness of insulating layer reduced and has positive charging region-to-source voltage whilst second FET is programmed - Google Patents

Abstract

The n-channel storage FET has the lower limit to the thicknes of its insulating layer reduced to allow small programming potentials, e.g. 17V at drain and 25V at gate, despite high negative charging, e.g. -7.5V. Small erase voltages, e.g. 17 or 20V at the charging area with OV at gate, are possible. The FET is intended for use in a programmable memory for a telephone exchange. Whilst a second n-channel storage FET, whose control gate is connected to the same control gate line as that of a first FET, is being programmed a potential which is positive w.r.t. the source potential is applied to the charging region of the first FET.

Description

n-channel memory FET

The invention is based on what is mentioned in the preamble of claim 1 n-channel memory FET with at least one gate, namely with one on all sides floating memory gate surrounded by an insulator, in which the memory gate is charged the electron-injecting channel injection - that is, recharging through one's own conductive channel strongly accelerated and thereby heated electrons, which because of their heating by an electric field acting in the source-drain direction Overcome the energy threshold to the conductivity band of the insulator and thereby to the Memory gate get - -us used, whereby the channel injection for programming, so charging of the memory gate is exploited, so that the memory gate after this Charging by means of its negative charge by influencing the source-drain current has an inhibitory effect on the source-to-end section, being a an additional controllable control gate having a connection is provided, which acts capacitively on the memory gate and which is connected to a control gate line 9 where the memory gate is conductive with a conductive tab over the at the electrical controlled erasure the discharge of the memory gate takes place9, whereby the tab at least a part of a semiconductor region serving to discharge the memory gate covered, the lobe of the semiconductor area covered by it by a thin Isolatorschisch is ternnt, the semiconductor area by one of the two Main corner connection areas isolated transfer area is formed and wherein the insulating layer between the tab and the transfer area thinner than between the memory gate and the channel area.

One such n-channel memory FET is disclosed by US Pat Main application P 26 43 987.2-33 proposed. The reloading area is referred to to a source potential of al volts, to erase strongly positive charge reversal potential and at the same time applied to the control gate, e.g. 0 volts, see also DE-OS 25 05 816.6 In the remaining times, there is another potential in the charge transfer area, e.g. the source potential from 0 volts.

All potential values given below relate to cases in which there is a 0 volt potential at the source.

In the main application it is already stated that the flaps isolator separating from the transshipment area layer thinner than that Insulator layer separating the memory gate from the channel region can be made, cf. also the somewhat similar p-channel memory FET in US Pat. No. 3,919,711. The thinner the lower the insulating layer between the tab and the transfer area are the positive minimum extinguishing potentials, which, especially for discharge of the storage gate by means of the Fowler-Nordheim tunnel effect, the reloading area of the relevant n-channel memory FETs are to be supplied. The n-channel memory FET thus constructed also normally works as intended with reduced extinguishing voltages between Flags and reloading area.

However, it was found that there was a layer between the thickness of the insulator the lobe and the transfer area of this first n-channel memory FET often a lower one There is a limit that cannot be fallen below, without a sometimes low, but sometimes also considerable disturbance in the operation of the first n-channel memory FET risk if its control gate is connected to the control gate of a second n-channel memory FET connected is.

The object of the invention is the lower limit of the concerned Shift the insulator layer thickness to even lower values, despite higher negative ones Charging, e.g. to -7.5 volts, of the programmed memory gate is particularly low Programming potentials - e.g.

Volts at the drain and e.g. 25 volts at the control gate - and at the same time special low erase voltages - e.g. 17 or 20 volts at the transfer area with 0 volts at the control gate - To be able to allow one and the same n-channel memory FET.

The invention is based on the introduction, as well as in the preamble of Claim 1 mentioned n-channel memory FET. The object of the invention is by the operation specified in the characterizing part of claim 1 solved that namely to the transfer area of this first n-channel memory FET during programming another, second n-channel memory FET, the control gate of which is conductive with the the same control gate line is connected, a positive compared to the source potential Potential is placed.

The invention will be described in more detail with reference to the two figures, the Each show a diagram of operating states of the n-channel memory FET. Included FIG. 1 relates to states of the n-channel memory FET according to the invention and FIG. 2 relates to states of an n-channel memory FET, its charge transfer area potential during programming of the second n-channel memory FET, contrary to the rule according to the invention, equal to the source potential O volts is.

The foundations of the new thoughts leading to the invention will be initially explained with reference to FIG.

This Figure 2 shows characteristics of a non-programmed (G10)) and of a programmed (G1n) n-channel memory FET example according to the preamble of claim 1 when the mode of operation is not in accordance with the invention. That is on the abscissa Control gate potential UG2 and in the ordinate the e.g. occurring memory gate potential UG1 specified. The programmed memory gate, see G1n, is here at -7.5 volts charged compared to the programmed memory gate, see G10. The rag lies at the same potential as the memory gate that is conductively connected to it. It it is assumed that at the reloading area, deviating from the invention Teach; 0 volts. It is also assumed that 25 volts are applied to the Sturgatc can, so A = +22 volts can be on the uncharged storage gate without one Fowler-Nordheim-Tunnelfect between the Lappen and the reloading area through the adjacent one To trigger voltage ULmin. The insulating layer between the rag and the transfer area must therefore be at least as thick, e.g. at least 35 nm, so that the The voltage ULmin applied there cannot trigger a Fowler-Nordheim-Tunnl effect.

But you make the insulating layer between the cloth and the transfer area even thinner, e.g. with a particularly small positive potential at the transfer area and 0 volts on the control gate, a discharge of the memory gate of the first n-channel memory FET to be able to carry out, then when programming the second n-channel memory FET, whose control gate is conductively connected to the control gate of the first n-channel memory FET is, more or less large disturbances of the first, so far also not programmed anal memory FETs occur: if you place it on the control gate of the second n-channel memory FET, to program this second n-channel memory FET long enough - each according to the exemplary embodiment, for example, a few msec long - a positive potential of e.g. of +25 volts, then during this programming period on the control gate of the first n-channel memory FET also +25 volts. The first n-channel memory FET thus has because of the capacitive coupling between its control gate and memory gate high voltage ULmin, here +22 volts, between its lobe and its transfer area on which this first n-channel memory FET, because of the insufficient thickness the insulating layer between the rag and the reloading area an often undesirable Fowler-Nordheim tunnel effect draw see also DE-OS 24 45 091 and 25 05 824. This effect causes electrons from the charge transfer area to the tab and thus to the memory gate flow and this more or less negative to load. The first, not too programming n-channel memory FET is thus, by programming the second n-channel memory FET, also programmed to a greater or lesser extent, -Possibly. so strong that it bothers. For any given insulator thickness between lobes and transfer area there is a limit potential A or UG2 with OV volts at the transfer area, if this is exceeded, such a fault, because of the voltage ULmin at the relevant Insulator layer, can occur.

There is another one on the programmed first n-channel memory FET Limit value ULmax of the transfer area potential. If namely +25 volts at the control gate e.g. because the second n-channel memory FET is just being programmed, then the transfer area potential should not be the sum of the storage gate potential, here +14 volts, plus ULmin, here +22 volts, do not exceed the sum ULma here = Exceed +38 volts0 Otherwise, a Fowler-Nordheim tunnel effect would occur between Tabs and reloading area triggered, with electrons from the storage gate via the tabs would flow to the transfer area, with a more or less strong discharge of the memory gate would be triggered.

From this follows the technical rule9 that at the transshipment area in general a less positive potential than ULmax should be - an extremely high limit value, which is hardly ever used anyway.

So is the thickness of the insulator between the flap and the transfer area made too low, in particular to get by with small erasing voltages, then the memory gate of the first, non-programmable n-channel memory FET, which, in particular in a matrix arrangement, when programming the second n-channel memory F-E Strongly positive control gate programming potential via the same control gate line received by a Fowler-Nordheim electron emission from the transfer area towards the storage gate received a negative charge, one more or less fakes strong programming of the n-channel memory FET in question.

To avoid this disruption, a reduction in the thickness of the insulator layer was necessary A lower limit is set between the rag and the transfer area, depending on the choice of the different ones Operating potential e.g. 30 nm, which in turn operates at UG2 = 0 volts with still relatively high reloading potential, e.g. 3. 22 volts, possibly even up to 35 volts am Reloading area.

In Fig. 1, the characteristic curve G10 again corresponds to the unprogrammed one State, i.e. in this example according to the invention one that is not yet negatively charged Storage gate. This characteristic curve G10 again shows the dependency of the in the ordinade plotted storage potentials UG1 from those plotted in the abscissa Control gate potentials UG1. Because of the very high self-capacitance assumed here between the control gate and storage gate compared to the relatively small self-capacitance the potential differs between the memory gate and the source-drain path of the uncharged storage gate is only slightly different from the potential of the control gate. Included it must be ensured again that the same potential is applied to the tab as to the storage tank gate, because the tab is connected to the memory gate in an electrically conductive manner. Between the flap and the loading area underneath the flap is at the for the mode of operation provided by the invention at least for the duration of the programming of the second n-channel memory FET has a lower voltage than that between the memory gate and the source. This is because the positive potential shown in FIG. 1 is located at the transfer area UV, here +7.5 volts.

For example, assuming, see Figure 1, that during programming of the second n-channel memory FET +25 volts at the control gate of the second n-channel memory FET lie gen, so that UG2 = +25 volts at the control gate of the first n-channel memory FET lie9 then lie in the present exemplary embodiment on the uncharged memory gate A22 volts; furthermore, the difference between these +22 volts and W5 is 1495 volts9 as tension between the flap and the transfer area0 would, however, be at the transfer area9 during the programming of the second n-channel memory FET different from the fiction according to the rule, instead of the potential UV = +7.5 volts, only a potential UV = 0 volts 9 would then be between during programming of the second n-channel memory FET the lobe and the charge transfer area of the first n-channel memory FET fully the voltage between the source and the memory gate, here +22 volts9 are 0 due to the fact that according to the invention a positive potential during programming of the second n-channel memory FET UV is at the transfer area, so there is a lower voltage on the thin insulating layer between the lobe and transfer area of the first n-channel memory FET as if the recharging area would be at 0 volts. Because because of the invention provided positive potential UV am Reloading area the voltage over the relevant thin insulating layer is considerably less than when at the transfer area If at the same time there were only 0 volts potential, it is possible to have a particularly low one Thickness of the relevant insulating layer between the tab and the transfer area allow: The relatively small voltage of im occurring in the invention In the present example ULmin = 14.5 volts because of the positive charge transfer area potential UV so low that even with particularly thin layers of insulation between the cloth and Reloading area, e.g. approx. 25 nm thick, just no Fowler-Nordheim-TunnelesSekt can occur.

On the other hand, the source potential would only be 0 volts at the charge transfer area the programming of the second n-channel memory FET, i.e. at UG2 = 25 volts, are present, then there would be an insulating layer thickness of 25 nm between the tab and the transfer area normally trigger a Fowler-Nordheim tunnel effect in such a way that Electrons from the transfer area through the insulating layer to the lobe and so that memory gate penetrate.

Such partial or total charging of the storage gate with Electrons would simulate programming of the first n-channel memory FET can, although in truth only the second n-channel memory FET has just been programmed should be At W = 0 volts or if the insulator layer is too thin, i.e. at This Fowler-Nordheim tunnel effect would namely the characteristic G10 gradually shifted in the direction of the characteristic curve Gln. So would be too low Layer thickness at the first n-channel memory FET, the control gate potential UG2 is sufficient long, e.g. 1 sec long, +25 volts and therefore the La-opotential is initially +22 volts, then the characteristic curve G10 would be @@@@ during this second and so far down moved worth ½? £ -7ft '= u? L because of the growing nega- a charge of the memory gate just reaches the threshold value ULmin at which the Fowler-Nordheim tunnel effect ceases and under which the Fowler-Nordheim tunnel effect no longer occurs.

In the embodiment shown in Fig. 1 it was additionally assumed that the thickness of the insulating layer between the flap and the transfer area is just as great is that at the positive potential UV provided according to the invention, here +7.5 Volts, at the transfer area and 22 volts at the rag at +25 volts at the control gate no Fowler-Nordheim tunnel effect occurs.

One would therefore use the control gate potential UG2 with the storage gate uncharged make G10 greater than +25 volts according to the characteristic curve, see the limit potential A in Fig. 1, then on the one hand there would be lobes between the memory gate and thus also and the transfer area, on the other hand, are more than 14.5 volts0 This would correspond accordingly the Scharffur entered at the limit potential A shows the Fowler-Nordheim tunnel effect trigger through which electrons from the charge transfer area via the tabs to the storage gate reach.

After the negative charging of the storage gate by means of channel injection Characteristic curve G109 no longer applies, but characteristic curve G1n. This characteristic curve G1n is in the present example by 795 volts negative compared to the characteristic curve G10 postponed. The programmed n-channel memory FET and thus the negatively charged one The characteristic curve G1n corresponding to the memory gate is in the present example, namely um 7.5 volts, shifted so much down, away from the characteristic curve G10, that a clear one Assignment of the states G10 and G1n to a deleted n-channel memory FET (G10) and to a programmed n-channel memory FET (Glii) possible is. The threshold voltage of the control gate at which the source-drain path of the relevant n-channel memory FET conducts a current during reading, is namely sufficient strongly shifted to the positive, based on the threshold voltage of the control gate of the erased n-channel memory FET. Especially with an n-channel memory FET with An enrichment-type channel can then easily be defined by flowing or non-flowing one Resource-drain current clearly indicates whether the relevant n-channel memory FET programmed or not programmed. During all reading processes, e.g. in a Matrix, can have the same positive at the transfer area of this first n-channel memory FET Potential UV, here +7.5 volts, are independent of whether the first n-channel memory FET in turn read or not read. One when reading the first n-channel memory FET A slight positive increase in the memory gate potential that occurs cannot namely not trigger the disturbing Fowler-Nordheim tunnel effect.

In the example shown in Fig. 1, it is additionally assumed that the potential that is present during the programming of the second n-channel memory FET at The charge transfer range of the first n-channel storage FET is - here W = +7.5 volts, just like that it is great that no discharge caused by a Fowler-Nordheim tunnel effect of the negatively charged memory gate of this first n-channel memory FET over the tab is triggered towards the loading area, if this is simultaneously o volts at the control gate harvest n-channel memory FET is - see the limit potential B shown in Fig. 1. In this case, the voltage formed by the difference between B and W lies -ULmin, here with approx. 15 volts, between the cloth and the transfer area, so that an already programmed first n-channel memory FET not inadvertently again in whole or in part over his Flap is deleted9 if only the second n-channel memory = FET is to be deleted, if so at the control gates of these two n-channel memory FETs each Weil 0 volts9 at the recharging area of the first n-channel storage FET the potential UV = 7.5 volts - instead of maybe even just UV = Volts - and at the recharging area of the second n-channel memory = FET on, the deletion of this second n-channel storage FET effecting charge reversal potential from zOBo +15 to +20 volts lies0 The potential of +7.5 volts can not only be used when programming, but also when erasing the second n-channel memory FET at the reloading area of the first n-channel memory cher FET without charging the memory gate of the first n-channel memory FET to change. In the example shown in FIG. 1, the limit potentials Å and vglo B9 is therefore the thickness of the relevant insulator layer between the tab and the transfer area on the one hand5 as well as the recharge area potential UV, as well as the size of the negative charge of a programmed memory gate9 here -7.5 volts9 so coordinated that both when programming the second n-channel memory FET and when erasing of the second n-channel memory FET no unwanted charge reversal of the memory gate of the first n-channel memory FET takes place.

In general, one is used in series production, especially in the case of installation of the inventive n-channel memory FET in a large memory matrix, not choose exactly this coordinated insulation layer thickness explained with reference to FIG. 1, but a slightly larger insulator layer thickness. Thereby one achieves that in spite of Scattering of the insulator layer thickness values and thus despite scattering of the threshold voltages, in which a Fowler-Nordheim tunnel effect occurs, the reject quote remains tolerably low in the manufacture of the n-channel memory FET. One can to do this, make the relevant insulator layer thickness, e.g. 10% greater than the one based on 1 corresponds to the coordinated insulation layer thickness explained in FIG. This can the tension between the rag and the reloading area must be somewhat greater, here about be 10% larger before a Fowler-Nordheim tunnel effect started. Despite however, the insulator layer thickness chosen in this way is a bit too thick Favorable operating mode, at least when programming the second n-channel memory FET - if not also with its deletion -ein approximately in the middle between the two limit potentials A, B lying potential W is applied to the charge transfer area is, where the one limit potential is that potential A that is in the gelsöchten state G10, with the usual control gate potential for programming, occurs at the memory gate, and wherein the other limit potential B is that potential that is programmed in State G1n, at 0 volt control gate potential, occurs at the memory gate. Through a This is because such a potential W at the transfer area can easily be individualized in a matrix Write, read and delete bits or a word or whole words without the rest. Disturbing matrix. Only if the first n-channel memory FET itself is cleared then there is a much higher positive reloading potential at its reloading area to lay.

If you have to change the thickness of the insulator between the rag and the transfer area slightly larger than the coordinated thickness specified above, or if one makes a correspondingly slightly changed positive potential W to the transfer area is achieved one has the further advantage that the supply voltages of the n-channel memory FET or the chip containing it may have corresponding tolerances Supply voltage changes in voltage then also do not yet have an effect such disturbances caused by the Fowler-Norheim tunnel effect.

When the first n-channel memory FET is erased, its charge transfer area potential also increase in a sawtooth shape in a positive direction, which may result in an overlaid avalanche breakthroughs between the transfer area and the substrate can be avoided, see DE-OS 25 25 097 = VPA 75 P 6106.

A line-by-line deletion of written words is possible, e.g. if the reloading areas and the control gates are each connected to one another line by line are, so that the transfer areas in each line with a common transfer area potential can be controlled. To do this, you just lay in the transshipment areas of the to be unloaded Line of the matrix, a charging area potential9 causing the erasure, e.g. about 17 Volt0 The deletion was previously described in operating states where at the same time the source potential, namely 0 volts, is applied to the control gate. Basically however, it is also possible to apply positive potentials to both the reloading area when extinguishing as well as to the control gate and at the same time to the source 0 volts and on to apply the drain e.g. also 0 volts. This mode of operation is also shown in FIG. If, for example, there is a potential UG 2 = +25 volts at the steering wheel9 then you have to go to the reloading area of the n-channel memory FET example explained by FIG. 1 apply a potential, which is greater than ULmax, e.g. in this case +37 volts.

In this case lies between the flap and the transfer area again a voltage which, at least at the beginning of the erasure, is about 8 volts higher as | ULmin |, here | ULmin | = approx. 15 volts. This reloading potential +37 As described above, volts are sufficient to produce a complete Fowler-Nordheim tunnel effect discharge of the memory gate, namely the memory gate state Gin in the memory gate state GIO passes over.

If, as usual, the n-channel memory FET is mounted on a chip is, there are also voltage drops in when dimensioning the operating voltages the other circuits mounted on the chip must be taken into account. The chip even voltages are to be supplied, each of which is higher by these voltage drops are than the voltages directly supplied to the n-channel memory FET.

The actual channel of the n-channel memory FET can be almost any be designed. He is supposed to be reliable in particular the channel injection for programming with particularly low positive potentials.

For example, the channel according to DE-OS 25 13 207 can also be different controlled parts can be divided or according to the proposal in the not yet published DE-OS 27 44 113 = 77 P 6215 be constructed.

Claims 2 figures

Claims (5)

Claims n-channel memory FET with at least one guest, namely with a floating memory gate 9 surrounded on all sides by an insulator in the case of the electron-injecting channel injection to charge the storage gate - that is Reloading through strongly accelerated and thereby heated up in its own conductive channel Electrons which, because of their heating, act in the source-drain direction electric field overcome the energy threshold to the conductivity band of the insulator and thereby get to the memory gate - is exploited, whereby the channel injection for programming9 thus charging of the memory gate is used, so that the memory gate after this charging by means of its negative charge by influencing the source-drain current acts inhibitory manner on the source-drain path, with an additional, a Terminal having controllable control gate is provided, which is capacitive the memory gate acts and which is connected to a control gate line, wherein the memory gate lei tend with a conductive tab, over the electrically controlled Erasing the discharge of the storage gate takes place, connected to the lobe at least part of a semiconductor region serving to discharge the memory gate covered and wherein the tab of the semiconductor region covered by it by a thin insulator layer9 with the semiconductor region separated by one of the two main line connection areas isolated transfer area is formed and wherein the insulator layer between the tab and the transfer region is thinner than between the memory gate and the anal area is, after registration P 26 43 987.2-33, in particular for the program memory of a telephone switching system, g e k e n n n z e i c h n e t d u r c h its mode of operation, that is to the transhipment area this first n-channel memory FET while programming another, second n-channel memory FET, the control gate of which is conductive with the same control gate line is connected, a potential (W) which is positive with respect to the source potential will. 2. n-channel memory FET according to claim 1, g e k e n n -z e i c h n e t d u r c h its mode of operation, namely that when programming the second n-channel memory FET one approximately in the middle (W in Fig. 1) between two limit potentials (A, B) Potential is applied to the charge transfer area, with one limit potential (A) being the Potential (+22 volts) is that in the deleted state (mio) for programming usual control gate potential (+25 volts) occurs at the memory gate, and the other limit potential (B) is the potential (-7.5 volts) in the programmed state (min), with the control gate potential identical to the source potential (0 volts), am Memory gate occurs. 3. n-channel memory FET according to claim 1 or 2, g e -k e n n z e i c h n e t d u r c h its mode of operation, namely when erasing on its control gate Source potential (0 volts) is applied. 4. n-channel memory FET according to claim 1 or 2, g e -k e n n z e i c h n e t d u r c h its mode of operation, namely that positive potentials when erasing both to the transfer area (+29 volts) and to its control gate (+25 volts) to the source potential of 0 volts. 5. n-channel Speiche.rFET according to claim 19 2 or 3, g e k e n n z e i c h n e t d u r c h its mode of operation, namely at its reloading area also during the deletion of the second nchannel = memory FET the same positive Potential (UV) is behind 6. n-channel memory FET. one of the preceding claims, g e k e n n n z e i c h n e t d u r c h its mode of operation, namely that also during Reading processes the same potential (UV) is at its transfer area.