DE2510113A1 - Direction detector for bar coding plate - has photodiodes with output pulses processed without differentiation to avoid ambiguity from noise - Google Patents

Abstract

The direction detector detects the pulses produced from photodiodes as an illuminated bar coding plate passes by and computes the direction of motion. Two samples are taken: the firt (A) is passed to a first trigger (7) and the second (B) to third and fourth triggers (9, 10). The outputs of the triggers are processed by logic circuitry to give difference signals and are used to provide a signal for the counter (15) that tells it in which direction to count. The advantage of this detection circuit lies in determining direction of motion without differentiating the output pulses and the circuit is consequently less sensitive to noise. It may also be produced as a MOS IC.

Description

Method and circuit arrangement for digitally measuring a distance with the help of an up and down counter.

The invention relates to a method for digitally measuring a distance, which is periodically subdivided into so-called increments, with a scanning element by relative movement generates periodic pulses along the path according to the periodic subdivision, which are counted by a counter, and where to detect the direction of movement the scanning element consists of two parts, either by spatial displacement against each other by a quarter period of the subdivision of the distance or by Sampling of two parallel subdivisions offset from one another by a quarter period provide two pulse series as scanning signals that are mutually timed by one Quarter period are offset and by logical connection via a discriminator the counter corresponding to the direction of the relative movement of the scanning element, the counting direction indicate.

Such a method is known and is, for example, called "incremental" Distance measuring method "in the" Guide to electronic control and regulation technology " Part II, Francis-Verlag? 4ünchen, 5. 30-33. The distance to be measured is divided by a line grid as a pulse scale. When observing will Along the way, an illuminated abbot plate, which contains two reading tracks. Each of the two traces of depth is subdivided by several columns, with the column of the first t-ese track against the gap of the second I read track by half a gap width are offset. Each of these two tracks is from one of their own Read photodiode. If the scanning plate moves over the scale, then deliver the two photodiodes after a pulse formation two RechX Imy rows, which are against each other around the h & Ibe Imsulsbrelte are offset. us the course of the two pulse series you can determine the direction of movement of the scanning plate.

Technically, this recognition of the direction of movement is in a discriminator accomplished in which the maximum value of a series of impulses is simultaneous with the the change value taking place in the other pulse series is compared. This change value is obtained by differentiation.

It is not only disadvantageous that this incremental measuring method is sensitive to interfering impulses as it is also on page 32 of the cited literature reference is given, but also that in the implementation of such a discriminator circuit in MOS technology as an integrated circuit due to the necessary differentiation Difficulties arise.

From the many integrating parallel capacities in a MOS-integrated Circuit results in very poor edge steepness, which leads to differentiation make more difficult. About that. in addition, the integral of the differentiating impulses would still have to be sufficient be large so that the logic gates respond. It could be a kind of pseudodifferentiation take place in that an undelayed signal with a delayed logic is combined. This delay can be done by an integrating capacitor.

But that means a lot of space is required. In addition to still bad edges of the pulses due to switching capacities is also disadvantageous, that this pseudodifferentiation is impossible if the impulses are too short because of the logic element the instantaneous signal on arrival of the delayed no longer has sufficient effect Has.

The present invention is based on the object of a method and to specify a circuit arrangement for incremental distance measurement, in which the Detection of the direction of movement without differentiation of pulses takes place and a Realization as an integrated circuit in MOS technology is possible.

To solve this problem, in a method according to the invention proposed that the first sampling signal via a first threshold switch with an upper threshold value to the first maximum value pulses during the maxima of the first sampling signal is shaped at the same frequency that the second sampling signal to a third and fourth threshold switch with an upper and with one lower threshold value is given, the output signals via a NOR operation to second differential pulses during the rise and fall of the second sampling signal and thus be formed with twice the frequency that the logical value in each case one pulse of the first maximum value pulse is held at the time of the next Pulse of the second differential pulse with the logical value of the next pulse the first maximum value pulses is linked and an identification signal K is obtained therefrom which indicates the counting direction to the counter, with the same in consecutive Value of the first maximum value pulses the counting direction is switched.

An advantageous further development of a method according to the invention relates to the so-called quadruple evaluation, where, in the example of the above To remain in the literature, four pulses per gap in the scanning plate are sent to the counter Counting is given in contrast to the double evaluation where only two pulses are given are to be counted per gap. This advantageous development is characterized by that the first sample signal not only on the first threshold switch but also on a second threshold switch with the lower threshold is given whose output signals via a NOR gate to first differential pulses during the rise and fall of the first sample signal are shaped that the logical value of a pulse of the second, the third threshold value switch maximum value pulses taken at the time of the next pulse the first differential pulse with the logical value of the next pulse of the second Maximum value pulses is linked and the pulses obtained from it in addition to the Time of the second difference pulses obtained pulses to the identification signal for the counting direction of the counter can be processed.

A circuit arrangement according to the invention for performing the according to the invention The method is characterized in that the discriminator is a first delay master-slave flip-flop with a D input, a T input and with an output that contains the first Maximum value pulses at the D input and the second difference pulses at the T input as Clock pulses lie that the D input with em output via an EXCLUSIVE OR gate is logically linked and that the output of the EXCLUSIVE-OR gate is via a negation element is logically linked to the T input in an AND gate, with the output of the AND gate pulses to the B of the identification signal are taken.

In a circuit arrangement according to the invention for performing the The method in the above-mentioned development for quadruple evaluation contains the Discriminator a second delay master-slave flip-flop, at whose D input the second Maximum value pulses and at its T input the first differential pulses are and where the D input and the output are connected to each other via an EXOLUSIVE OR gate and the output of the EXCLUSIVE-OR gate a negation link and the T input are logically linked to one another in an AND gate, where the output of the AND gate with the one from the second delay master-slave flip-flop pulses obtained and the output of the AND gate with those from the first delay-vice-slave-flip-flop The pulses obtained are linked to one another via an OR gate to form an output for pulses that are processed into the identification signal.

In both cases, the AND gate or the two is advantageous AND gate linking OR gate is followed by a trigger flip-flop, its The output state is switched over by the input pulses and the identification signal forms. This gives a static input command for the counter in which direction he has to count. The initial state of the trigger flip-flop and thus the counting direction of the counter is switched every time when changing the direction of movement in the case of one of the two maximum value signals, two maxima or two minima on top of one another follow. In the case of the quadruple evaluation, it must be prevented that the one the output pulse of one AND gate that triggers the switchover with the same direction of movement The following output pulse of the other AND gate triggers a switchover again.

At this point it should also be mentioned that beneficial to a safe Counting should be guaranteed that the counting bars between the possible Change of the identification signal triggering impulses, i.e. not simultaneously with one possible switching of the counting direction. It should also be mentioned here that it is irrelevant whether the scanning element moves with respect to the path, or whether the path moves with respect to the fixed scanning element. The decisive factor is Relative movement.

With the figures in the drawing, the invention is intended to be followed by further Details are explained in more detail. 1 shows schematically in a block diagram the entire arrangement with the scanning element, the pulse conversion, the discriminator and with the counter. In FIG. 2, the time courses of the occurring Impulses shown. 3 shows the circuit implementation of the Pulse shaper, the Fig. 4 in a block diagram the discriminator circuit for the Double evaluation and the vi £. 5 for the quadruple evaluation. Fig. 6 contains the technical structure of the discriminator according to FIG. 4 with logic modules.

In Fig. 1, 1 and 2 are two incrementally subdivided tracks a and b denotes, the opposite of each other in the one shown by a double arrow Direction of movement are offset by a quarter period of the incremental division. An optical scanning element is formed by two photodiodes 3 and 4, the Photodiode 3 a received from the track 1 optical signal to an electrical Output signal and the photodiode 4 an optical signal picked up by the track 2 convert it to an electrical output signal. It is assumed in this representation, that the scanning element with the photodiodes 3 and 4 is stationary, while the two Tracks 1 and 2 in the directions of movement indicated by the double arrow can move. The photodiode 3 is an amplifier 5 and the photodiode 4 is an amplifier 6 downstream. The output signal A of the amplifier 5 leads to two Schmitt triggers 7 and 8, the output signal B of the amplifier 6 leads to two Schmitt triggers 9 and 10. The two Schmitt triggers 7 and 9 have an upper response threshold S1, the two Schmitt triggers 8 and 10 have a lower response threshold S2.

The output signals of the Schmitt triggers 7 to 10 are one after the other denoted by A1, A2, B1,32 The two output signals A1 and Ä 2 of the two Sohmitt triggers 7 and 8 become a signal IA in a NOR gate 11, the two output signals B1 and the two Schmitt triggers 9 and 10 in a NOR gate 12 to form a signal 13 shaped. The two signals A1 and B1 are so-called maximum value pulses, i.e. around the point in time of the maximum value of the two signals A and B, namely from one Width determined by the upper threshold S1. The two signals and 32 are negated maximum value pulses around the point in time of the maximum of the two signals A and B and their width is defined by the lower threshold value S2. By the link in the two NOR gates 11 and 12 are the signals 1A and Ig here so-called.

Differential pulses at times when the two signals A and B move between the two thresholds S1 and S2, respectively. The maximum value pulses A1 and B1 and the two differential pulses 1A and 13 are one on four inputs Discriminator 13 given. The two difference pulses IA and 13 are in an NCR gate 14 linked and converted to counting clocks ZT for a counter 15. The discriminator 13 forms an identification signal K from its input signals to determine the counting direction of the counter 15.

This is initially the entire block diagram for the quadruple evaluation. For the double evaluation, the threshold value switch 8 and the NOR gate 11 fall path. The NOR gate 14 is then a negation. Only those are the discriminators Signals A1 and 13 supplied; its internal structure is simpler. For representation in this case, the threshold switch 8, the NOR gate 11 and the signals 2 and 1A leading connecting lines as well as the input line of the discriminator 13 drawn in dashed lines for the signal B1.

The course of the signals mentioned results from the representation in Fig. 2. It is first the periodic subdivision of the two tracks a and b shown, d '£ e are offset from one another by a quarter period. Further FIG. 2 shows the time course of the two supplied by the amplifiers 5 and 6 Signals A and B, approximately sinusoidal, with the two threshold values 1 and S2 the threshold switch 7 to 10.

This results in the time profile of the maximum value pulses A1, A2, B1, B2. The respective difference results for the signals 1A and 1B. that due to the offset by a quarter period difference pulses TA temporally with Maximum value pulses B1 and B2 coincide and differential pulses 13 with maximum value pulses A1 or A2. The difference pulses IA and 13. appear with twice the frequency the maximum value pulses; d. H. that also at the times of the minimum of the signals A and B difference pulses IB and IA take place. In each case at the point in time when turning a differential pulse I, but there is still a differential pulse IB, there is a pulse of the counting cycle ZT. At time t1, there is a change in the direction of movement. After the last counting cycle, the identification signal K is then changed, as shown in FIG Fall from zero to logical 1.

3 contains the circuit diagram of an advantageous one Realization of the threshold value switches 7 to 10.

The circuit for two threshold switches 7 and 8 or 9 and 10 shown. In these threshold value switches, the analog signals A and B form the digital pulses A1, and I2 or B1 and 2. Between two supply potentials VGG and VSS are two series connections made up of two drain-source paths MOS? E! Effect transistors 16, 17, 18 and 19 are placed. The gate electrodes are located here of transistor 1 and that of transistor 18 and. the source electrodes of the transistors 17th and 19 at the supply potential VGG and the drain electrodes of the two transistors 16 and 18 at the supply potential Vss. Teine vingangsklemme 20, which the signal A leads is connected to the gate electrodes of transistor 16 and transistor 19. The junction of the two transistors 16 and 17 and that of the transistors 18 and 19 each lead to the input of an RS flip-flop with the outputs 21 and 22nd

Output 21 carries signal I2 and output 22 carries signal A1.

The two RS flip-flops are each made up of two feedback NOR gates 23 to 26 implemented, the two RS inputs each via a negation element 27 and 28 are connected complementarily. For the signal B and the signals B1 and B2 the same applies.

In the series connection of the two transistors 16 and 17 is used Transistor 16 as a switching transistor and transistor 17 as a load transistor. Authoritative there is a single threshold voltage for switching this switching transistor 16 through, so that via the source electrode of transistor 16 and via the associated RS flip-flop the Xllsgang 21 then leads a pulse with the logic value 1, if the input signal A is below the lower threshold value S. The series connection of the two transistors 18 and 19 illustrate a switch with a higher threshold because the '"ranqistor 19 work as a switching transistor and the transistor 18 as a LæsttranFistor and the Transistor 19 then turns on when the input signal A has a higher threshold value exceeds. After this higher threshold value S7 is exceeded, the output leads 22 a pulse A1 with the logic value 1.

Fig. 4 shows the internal structure of the discriminator 13 for the The case of double evaluation, where at its input only one type of maximum value pulse A-1 and one kind of differential pulse TB are placed and the identification signal K is formed therefrom. win so-called delay master-slave flip-flop 29 has one input labeled D and one input labeled T. At input D, are the ttaximalv.ertimpulse A1 is applied to the input T the difçerenzinsulse TE. no Switching step of the flip-flop. 29, d. H. if the difference pulses 13 over the clock input switch the flip-flop 29, that of the maximum value pulses A1 is sent to the input D placed state is taken over in the flip-flop 29 and up to the next switching step kept, where the flip-flop 29 sets itself again after its input D. That means that at the time of a differential pulse 1B at the output of the flip-flop 2 & the value of the maximum value pulses A1 is that they were at the time of previous difference impulse 1B had.

In the normal case, where at the time of successive differential pulses 1B the Maxiinalwertiinpulse A1 have a changing logical value, show the Input D and the output of flip-flop 29 always have a different logic Value on. This applies to the case where the relative direction of movement of the tracks a and b and thus the counting direction of the counter 15 remains the same. Turns against it the relative direction of movement of the two tracks a and b by - the time t1 in 2 - then the value of the maxima value pulses A1 at the times of one Difference pulse 1B before the change of direction and the next difference pulse 1B immediately after the change of direction. Then run but at the time of this next Differential pulse IB the input D and the output of the flip-flop 29 have the same logic Value.

Inputs D and the output of the flip-flop 29 is given to an EXCLUSIVE-OR gate 30, which is connected to his The output then has a logic zero if the input D and the output of the flip-flop 29 either both have the value logical 0 or the value logical 1. The exit of the EXCLUSIVE-OR gate leads via a negation 31 to the a Input of an AND gate 32. The other input of the AND otter 32 is with the input T flip-flops 29 connected. Thus, the output of AND gate 32 only leads one Pulse before 'value lo i-ch 1, if the maximum value pulses A at the points in time are consecutive Differential pulses e. have the same value. The output pulse of the AND gate 32, which represents a signal for the counter 15 to switch the counting direction, is advantageously given to a trigger flip-flop 33. Such a flip-flop 33 switches its initial state changes whenever a pulse is applied to its input will. This initial state of the flip-flop 33 represents the identification signal for the counter 15 K represents.

In Fig. 5, the internal structure of the discriminator 13 is for the Quadruple evaluation shown. Corresponding to the two other inputs of the discriminator 13 of FIG. 1 for the maximum value pulses B1 and for the difference pulses IA the circuit according to FIG. 4 is expanded by a second delay master-slave flip-flop 34 with an input D and with an input T and with an output. At the entrance D are the maximum value pulses B7 and the difference pulses IA are applied to input T. The input D and the output of the flip-flop 34 are in an EXCLUSIVE-OR gate 35 linked, the output of which via a negation element 36 with the input T of the flip-flop 34 is linked in an AND gate 37. The output of the AND gate 37 is with linked to the output of AND gate 32 according to FIG. 4 in an OR gate 38 and a trigger flip-flop 39 is applied to the clock input. The output 40 of the trigger flip-flop 39 leads the identification signal K to determine the counting direction of the counter 15. In this In the case of quadruple evaluation, ZT can be caused by both differential pulses after each counting cycle IA and 1B the counting direction can be switched over. However, im Trigger flip-flop 39 can still be guaranteed that after switching that at the time For example, a differential pulse 13 has been triggered, not the new Direction of movement at the time of the subsequent difference 1, the output pulse that occurs again triggers a switchover.

aroh the NOR gate 14 according to FIG. 1 is guaranteed that e vshltsz'e ZT does not coincide with a switching pulse exemplary embodiment of the discriminator structure with logic gates shown. The basis for this is the block diagram according to FIG. 4 for the double evaluation taken. The extension to the quadruple evaluation according to the block diagram of Fig. 5 can be easily done.

Both the master part and the slave part of the delay master-slave flip-flop 29 each consists of an RS flip-flop made up of two NOR gates each with feedback 41.42 and 43.44, respectively. The R and S inputs for setting and resetting the flip-flops are each controlled via an AND gate 45 to 48. The input with the maximum value pulses A1 is connected to one input of AND gate 46 and via a negation element 49 to one Input of the AND gate 45 of the button part. The other inputs of the AND gates 45 and 46 are at the input for the difference pulses IB.

One input each of the two AND gates 47 and 48 of the slave part lie via a negation element 50 at the input for the difference pulses IB. The two other inputs of AND gates 47 and 48 are connected to the outputs of the two OR gates 41 and 42 connected.

The input with the maximum value pulses A1 is also present one input of an OR gate 51 and one input of a NAND gate 52. At the other two inputs of the OR gate 51 and the NAND gate 52 is the output of the OR gate 44 of the delay master-slave 91ipflop 29. The output the OR gate 51 and that of the NAND gate 52 are linked in a NAND gate 53, the output of which leads to one input of an AND gate 54. With the other entrance of the AND gate 54, the input for the differential pulses IB is connected. The configuration the gate 51 to 54 represents the EXCLUSIVE-OR gate with the negation element 31 and the AND gate 32 after the Pig. 4 represents.

The trigger flip-flop 33 is made up of an It2ster slave flip-flop, its silk parts also consist of two RS flip-flops with NOR gates and control are built up via AND gates.

he master part contains two feedback ICP gates 55 and 56, which are controlled via two AND gates 57 and 58. The slave part consists of two fed-back NOR gates 59 and 60, which have two AND gates 61 and 62 can be controlled. The output is used to control the trigger flip-flop 33 of the AND gate 54, each with one input of the two master AND gates 57 and 58 and is connected via a negation element 63 to one input each of the slave UID gates 61 and 62. The other two inputs of grid AND gates 57 and 58 are respectively with one of the two outputs of the slave flip-flop, i.e. the outputs of the two NOR gates 59 and 60 connected. The output of NOR gate 60 carries the Xenn signal K to determine the counting direction of the counter 15.

5 claims 6 figures

Claims (5)

P a t e n t a n s p r ü c h e S Method for digitally measuring a Distance that is periodically subdivided into so-called increments, with a scanning element by relative movement along the path according to the periodic subdivision periodic pulses generated, which are counted by a counter, and where for Detecting the direction of movement the scanning element consists of two parts, either by spatial offset from one another by a quarter period of the subdivision the distance or by scanning two parallel against each other by a quarter period staggered subdivisions deliver two pulse trains as scanning signals that oppose each other are offset in time by a quarter period and are logically linked over a discriminator to the counter according to the direction of the relative movement of the Scanning element indicate the counting direction, which is not shown -that the first sampling signal (A) via a first threshold value switch (7) with an upper threshold value (S1) to first maximum value pulses (A1) during the maxima of the first sample signal (A) is formed with the same frequency% that the second Sampling signal (B) to a third and fourth threshold value switch (9,10) with an upper and a lower threshold value (S1, S2) is given, their output signals (B1, B2) via a NOR link to second differential pulses (13) during the Rise and fall of the second scanning signal (B) and thus double Frequency are shaped that the logical value of each pulse of the first Maximum value pulses (A1) recorded, at the time of the next pulse the second Difference pulses (13) with the logical value 'of the next pulse of the first maximum value pulses (A1) is linked and from this an identification signal (K is obtained, which is sent to the counter (15) indicates the direction of counting, with the first successive value being the same Maximum value pulses (A1) the counting direction is switched. 2. The method according to claim 1, d a d u r c h g e k e n n -z e i c h n e t, ate to Zv'eok the so-called quadruple evaluation, where the counter (15) per period the path subdivision makes four counting steps, not only the first LbtPstsinal (i) on the first threshold switch (7) but also on a second threshold switch (8) is given with the lower threshold value, whose output signals (A1, A2) above a NOR gate (11) to first differential pulses (IA) during the rise and Falling of the first sampling signal (A) are shaped that the logic value in each case one pulse of the second maximum value pulses taken from the third threshold value switch (9) (31)) at the time of the next pulse of the first differential pulse (IA) with the logical value of the next pulse of the second maximum value pulses (21)) and the resulting impulses in addition to those at the point in time of the second difference pulses (in) obtained pulses to the identification signal (K) for the counting direction of the counter (15) can be processed. 3. Circuit arrangement for performing the method according to claim 1, that the discriminator (13) a first Delay master-slave flip-flop (29) with one input, one T input and one Output contains that the first maximum value pulses (A1) at the D input and the second Differential pulses (I) are at the T input as clock pulses that the D input with the output is logically linked via an EXCLUSIVE-OR gate (30) and that the Output of the EXCLUSIVE-OR gate (30) via a negation element (31) with the T input is logically linked in an AND gate (32), with the output of the AND gate (32) Pulses for forming the identification signal (X) are taken. 4. Circuit arrangement for performing the method according to claim 2, that the discriminator (13) has a second Delay master-slave flip-flop (34) contains the second maximum value pulses on its D ring (31)) and the first differential pulses (IA) are at its T input, .that the D-input and the output via an EXCLUSIVE-OR gate (35) with each other and the Output of the EXCLU3IV-OR gate (35) via a negation element (36) and the T input are logically linked to one another in an AND gate (37), the output of the AND gate (37) with the flip-flop (34) obtained from the second delay master-slave Pulses and the output of the AND gate (32) with the from the first delay master-slave flip-flop (29) obtained pulses via an OR gate (38) linked to one another Lead output for pulses that are processed to the identification signal (K). 5. Circuit arrangement according to claim 3 or 4, d a d u r c h g e k It is noted that the AND gate (32) resp. the OR gate (38) linking the two AND gates (32,37) a trigger flip-flop (39) is connected downstream, the output (40) of which the identification signal (K) leads.