DE2406578A1 - Verfahren zur herstellung integrierter halbleiterschaltungen - Google Patents
Verfahren zur herstellung integrierter halbleiterschaltungenInfo
- Publication number
- DE2406578A1 DE2406578A1 DE19742406578 DE2406578A DE2406578A1 DE 2406578 A1 DE2406578 A1 DE 2406578A1 DE 19742406578 DE19742406578 DE 19742406578 DE 2406578 A DE2406578 A DE 2406578A DE 2406578 A1 DE2406578 A1 DE 2406578A1
- Authority
- DE
- Germany
- Prior art keywords
- layer
- connecting conductor
- metal
- conductor matrix
- insulation layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US33151173A | 1973-02-12 | 1973-02-12 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| DE2406578A1 true DE2406578A1 (de) | 1974-08-15 |
Family
ID=23294273
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE19742406578 Pending DE2406578A1 (de) | 1973-02-12 | 1974-02-12 | Verfahren zur herstellung integrierter halbleiterschaltungen |
Country Status (4)
| Country | Link |
|---|---|
| JP (1) | JPS49114381A (cs) |
| CA (1) | CA1004779A (cs) |
| DE (1) | DE2406578A1 (cs) |
| GB (1) | GB1419906A (cs) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2137808A (en) * | 1983-04-06 | 1984-10-10 | Plessey Co Plc | Integrated circuit processing method |
-
1974
- 1974-01-29 JP JP49011567A patent/JPS49114381A/ja active Pending
- 1974-02-04 GB GB499574A patent/GB1419906A/en not_active Expired
- 1974-02-07 CA CA192,009A patent/CA1004779A/en not_active Expired
- 1974-02-12 DE DE19742406578 patent/DE2406578A1/de active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| GB1419906A (en) | 1975-12-31 |
| CA1004779A (en) | 1977-02-01 |
| JPS49114381A (cs) | 1974-10-31 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| OHJ | Non-payment of the annual fee |