DE2403641A1 - Verfahren zur herstellung von feinen mustern - Google Patents

Verfahren zur herstellung von feinen mustern

Info

Publication number
DE2403641A1
DE2403641A1 DE2403641A DE2403641A DE2403641A1 DE 2403641 A1 DE2403641 A1 DE 2403641A1 DE 2403641 A DE2403641 A DE 2403641A DE 2403641 A DE2403641 A DE 2403641A DE 2403641 A1 DE2403641 A1 DE 2403641A1
Authority
DE
Germany
Prior art keywords
layer
pattern
resist pattern
etched
etchant
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
DE2403641A
Other languages
German (de)
English (en)
Inventor
Douglas J Hamilton
Masamichi Sato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujifilm Holdings Corp
Original Assignee
Fuji Photo Film Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Photo Film Co Ltd filed Critical Fuji Photo Film Co Ltd
Publication of DE2403641A1 publication Critical patent/DE2403641A1/de
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D44/00—Charge transfer devices
    • H10D44/40—Charge-coupled devices [CCD]
    • H10D44/45—Charge-coupled devices [CCD] having field effect produced by insulated gate electrodes 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0198—Integrating together multiple components covered by H10D44/00, e.g. integrating charge coupled devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/482—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes for individual devices provided for in groups H10D8/00 - H10D48/00, e.g. for power transistors
    • H10W20/484—Interconnections having extended contours, e.g. pads having mesh shape or interconnections comprising connected parallel stripes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers

Landscapes

  • Solid State Image Pick-Up Elements (AREA)
  • Manufacturing Of Printed Circuit Boards (AREA)
  • Weting (AREA)
  • ing And Chemical Polishing (AREA)
  • Photosensitive Polymer And Photoresist Processing (AREA)
DE2403641A 1973-01-25 1974-01-25 Verfahren zur herstellung von feinen mustern Pending DE2403641A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP48010452A JPS5236675B2 (enExample) 1973-01-25 1973-01-25

Publications (1)

Publication Number Publication Date
DE2403641A1 true DE2403641A1 (de) 1974-08-01

Family

ID=11750521

Family Applications (1)

Application Number Title Priority Date Filing Date
DE2403641A Pending DE2403641A1 (de) 1973-01-25 1974-01-25 Verfahren zur herstellung von feinen mustern

Country Status (2)

Country Link
JP (1) JPS5236675B2 (enExample)
DE (1) DE2403641A1 (enExample)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2328288A1 (fr) * 1975-10-15 1977-05-13 Philips Nv Perfectionnements au procede pour fabriquer des dispositifs electroniques
EP0052920A3 (en) * 1980-09-25 1984-04-25 Texas Instruments Incorporated Electronic circuit interconnection system
DE102006035749A1 (de) * 2006-07-28 2008-01-31 Leonhard Kurz Gmbh & Co. Kg Verfahren zur Herstellung mindestens eines Bauteils sowie Bauteil

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2432719B2 (de) * 1974-07-08 1977-06-02 Siemens AG, 1000 Berlin und 8000 München Verfahren zum erzeugen von feinen strukturen aus aufdampfbaren materialien auf einer unterlage und anwendung des verfahrens
JPS54107675A (en) * 1978-02-10 1979-08-23 Matsushita Electric Ind Co Ltd Manufacture for semicnductor device
JPS5669835A (en) * 1979-11-09 1981-06-11 Japan Electronic Ind Dev Assoc<Jeida> Method for forming thin film pattern
JPS5687326A (en) * 1979-12-17 1981-07-15 Sony Corp Method of forming wiring

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2328288A1 (fr) * 1975-10-15 1977-05-13 Philips Nv Perfectionnements au procede pour fabriquer des dispositifs electroniques
EP0052920A3 (en) * 1980-09-25 1984-04-25 Texas Instruments Incorporated Electronic circuit interconnection system
DE102006035749A1 (de) * 2006-07-28 2008-01-31 Leonhard Kurz Gmbh & Co. Kg Verfahren zur Herstellung mindestens eines Bauteils sowie Bauteil

Also Published As

Publication number Publication date
JPS5236675B2 (enExample) 1977-09-17
JPS4999274A (enExample) 1974-09-19

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