DE2355361A1 - Adjustment device for an analogue signal digital display - has an analogue-digital converter with a signal integrator and a counter - Google Patents

Abstract

The counter displays the converter digital outputs. It has further a controlled electronic switch in the analogue signal input, whose keying ratio is determined during at least one adjustment cycle. It comprises: a) adder for addition of a number corresponding to the counter reading difference from the required value, to the content of a first shift register; b) a second counter which takes over the modified shift register content, to whose backward counting input counting pulses are applied until it returns to zero; c) a bistable flip-flop, set by a signal controlling the second counter taking over the shift register content, and reset when the second counter reaches zero. It controls the electronic switch previously noted.

Description

Diploma Phys. JÜRGEN WEISSt · DipI.-Cht-m. Dr. RUDOI F WOLGAST

D 5602 LANGENBERG BÖKENBUSCH 41 Postfadi86 Telephone: (02127) 4019 Telex: 8516895.

Patent application

Bodenseewerk Perkin-Elmer & Go. GmbH., Überlingen / Lake Constance

Device for adjusting the digital display of an analog signal

The invention relates to its gate direction for comparing the digital Display of an analog signal, containing an analog-to-digital converter with signal integrating means and a counter in which the digital output of the analog-digital converter appears, as well as an analog signal input influencing this output, in which is a controlled electronic switch which has a pulse duty factor determined during at least one adjustment cycle is controllable "

It can be a device for automatic zero point correction act a digital display device, in which a measuring signal input of the analog-digital converter is a flow signal superimposed, analog correction signal can be applied. By background signals or hull point drift of a signal processing Switching can also occur on the digital display device when there is actually no signal at the input of the analog-digital converter and the display device should display Full, an "empty signal" should be present. This empty signal can be superimposed a correction signal at the measuring signal input can be compensated,

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so that a measurement signal can then be displayed without zero point errors ₀

However, it can also be a comparison of the digital display of a analog signals act in such a way that a predetermined digital display corresponds to a predetermined analog input signal. In the case of an atomic absorption spectrometer, for example, a calibration sample can be sprayed into the flame which has a concentration contains a searched item of $ 10. This calibration sample is generated a certain analog signal at the input of the analog-digital converter "It is desirable that this analog signal the Display "10" corresponds.

It is known (DT-OS 2 009 527) to arrange a controlled electronic switch at an input in an analog-digital converter that works with a temporal integration of an analog signal to be converted ₀ In this known arrangement, the logarithm of the ratio of a measurement and a reference signal is formed, with the measurement and reference signal being determined by the intensities of a sample and a reference _{light beam in a two-beam spectrometer o} In the absence of sample in the sample light beam the two signals should be the same. A deviation is corrected by changing the pulse duty factor of a controlled electronic switch provided at the signal input of one signal. The switch is controlled by a bistable toggle stage. The bistable multivibrator is in turn set and reset by a pair of counters to which a common counting frequency is applied via frequency dividers, a residual signal appearing during a zero calibration cycle being converted into a pulse train and this pulse train depending on the sign of the residual signal in one or the other other counter is counted, so that a corresponding "phase shift" of the two counters against each other and thus a time difference

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reached between setting and resetting of the bistable multivibrator will «, This arrangement is quite complicated and time-consuming.

The invention is based on the object .a circuit arrangement to create which with relatively simple means an automatic adjustment of the digital display in a device of the ■ the aforementioned type depending on the output of the analog-digital converter allowed

According to the invention, this object is achieved by:

a) means for adding a number which corresponds to the deviation of the respective counter content of said (first) counter of a desired value corresponds to the content of a (first) shift register,

b) a second counter into which the content of said (first) shift register modified in this way by means of a transfer pulse can be read in and its "down" input is applied with a counting frequency for blank counting of the counter is and

c) a bistable zipper, which by the takeover signal settable and by an empty counting signal when empty counted Counter can be reset and through which said electronic switch can be controlled «,

The basic idea of the invention is that the deviation the actual display of a desired display in more appropriate Way formed and thus the content of a shift register is corrected. The content of the shift register corrected in this way is displayed on transmit a counter. The counter runs at a fixed frequency

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counted empty, and for the duration of this empty counting process a bistable trigger circuit set. The bistable multivibrator controls a switch at the input of the analog-digital converter, wherein the input signal according to the duty cycle of the "bistable flip-flop is modified. The actual value changed in this way is again with a desired display (which can be ITuIl) compared and changed the content of the shift register again according to the difference »This change in the content of the Shift register and thus the change in the duty cycle the bistable multivibrator and the controlled electronic switch takes place in successive balancing cycles with converging ones Steps until the desired adjustment has been made »

The method described can be used both to accomplish a zero adjustment, ie to use the digital one in the case of an "empty signal" Get Ad Hull. However, the method can also be used for calibration to a given analog input signal assign a predetermined desired finite display.

The said "means for adding "have a second shift register, in which at the beginning of each adjustment cycle with an empty signal at a measurement signal input of the analog-digital converter, the content of the first counter can be read is, as well as an adder, at the inputs of which the series outputs of the first and the second shift register are present and whose output is connected to the serial input of the first shift register «. Via the controlled electronic switch, a constant voltage can be applied to an integrator whose output forms an analog correction signal superimposed on the analog measurement signal.

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in the absence of a measurement signal at the measurement signal input an empty signal occurs, then a number corresponding to this empty signal results in the first counter. This counter reading is transferred to the "second shift register. The content of the first shift register is initially Hull. The individual bits from the first and the second shift register are now fed serially to the adder and the sum obtained, i.e. the content of the second in the first cycle The content of the first shift register is then transferred to the second counter. The second counter therefore contains a number which is equal to the digital display of the "empty signal". The second counter is then set at a fixed frequency l.eerge counts “During this idle counting process, the bistable flip-flop is set and closes the controlled electronic switch, so that the said voltage is applied to the integrator and the integrator output voltage increases linearly. The final value of the integrator output voltage is proportional to the time during. which the bistable flip-flop is set and thus or _o proportionally to the count of the second counter o The integrator output is superimposed as correct voltage on the empty signal from Keßsignalingang -

In the next zero adjustment cycle, the output of the analog-digital converter is therefore reduced compared to the first cycle. This reduced output; is transferred to the second shift register, added by means of the adder to the contents of the first shift register resulting from the previous cycle, so that the sum of the zero point counters from the first and second cycle is then read into the first shift register the second counter is transmitted, the second counter is counted empty with a fixed counting frequency and the bistable flip-flop v / lrd for the. Duration of the empty counting set in order to apply the integrator to the voltage for the generation of the ^ o: 're]; turvoltage for a corresponding time. This process kc, nn nehrfs-ch

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repeat, with the respective contents of the second shift register the actual value of the signal voltage is added in each case. Due to the liorrelcturspannimg this actual value is constantly smaller, so that the display converges on a fourth ITuIl "

To adjust the digital display of an analog signal in such a way that a given analog input signal has a given The device can be characterized by:

a) a shift register into which the contents of the count can be transferred at the beginning of each calibration cycle,

b) a shift register with a series output traced back to its series input, into which the said predetermined digital display can be read in parallel ₉

c) an adder connected to the serial subtraction, whose inputs are connected to the series outputs of the two shift registers are connected and its output to the series input of a shift register is switched

d) a shift register whose series input is connected to the output of an adder, the both inputs of the adder with the series outputs of the two last-mentioned shift registers are connected and the content of the last-mentioned shift register can be read into a counter that can be counted empty are set through which a bistable flip-flop to control the electronic switch and is reset ,,

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In such an arrangement, a shift register contains the counter contents at the beginning of the calibration cycle. Another shift register contains the "setpoint", that is to say the specified digital one Advertisement. The difference between the actual value and the setpoint is formed and read into a shift register »The next step within of an adjustment cycle consists in correcting the content of a shift register with this difference between the actual value and the setpoint value which is then transferred to the counter that can be counted empty and the switching duration of the bistable multivibrator and the controlled electronic Switch specific *

Usually, in this operation, the initial state, d _o h. the content of the last shift register must be such that initially the measuring voltage can be continuously applied to the input of the analog-digital converter. The display should then be larger than the desired digital display. The content of the shift register is then reduced by the difference between the actual value and the setpoint value, so that the measurement voltage is switched off from the input of the analog-digital converter for a time proportional to this difference and the actual value is reduced accordingly. This process is repeated in successive adjustment cycles with decreasing differences between the actual value and the nominal value, with the digital display converging to the desired predetermined value

The device is now calibrated and the measurement can then be carried out with an unknown measuring voltage using the same duty cycle to control the electronic switch » This duty cycle is saved in the one with the empty-countable Counter connected shift register, and the contents of this shift register is again in the counter for the control during the measurement the bistable flip-flop "

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A single adder can be provided to save τοη components be, and it can be by a switching device that during a first part of each calibration cycle in a first switching state and into one during a second part of the alignment cycle second switching state is switchable, an input of the adder im first switching state of the switching device with the series output the shift register storing said predetermined digital display and, in the second switching state, with the series output of the; Be connected to the shift register, the content of which is in the empty-countable Counter can be read. It can still be in a single shift register, whose series input is connected to the output of the adder and whose series output is connected to the other input of the adder, once the count of the output of the analog-digital converter forming counter can be read in parallel and then the difference between this counter reading and said predetermined The number corresponding to the digital display can be read in serially from the output of the adder.

Finally, a single adder can be used for zeroing and calibration be provided, one input of which is in a third switching state the switching device with the series output dee first Shift register of the zero adjustment device and whose output is connected to the series input of this shift register.

The invention is explained in more detail below using an example embodiment with reference to the accompanying drawings

Pig. 1 shows a block diagram of an inventive Circuit arrangement «

Pig. 2 shows a slightly more detailed block- ' circuit diagram. '

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At a measurement signal input 10 of an analog-digital converter 12 if there is an "empty" signal during a hulling cycle, i. a signal which * should ideally be zero, because for example no sample has yet been placed on an atomic absorption spectrometer delivering the measurement signal was given, but this was due to the background signal and / or Hull point drift of the signal processing control a finite ¥ ert fcat. The analog-to-digital converter provides one Sequence of pulses, the number of which is proportional to the empty signal present is · These pulses are counted into a counter 14. At the same time there is a display on a display device 16,

The count of the counter 14 is transferred to a shift register 18. The shift register 18 is connected to an adder 22 via line 20. A shift register 26 is also connected to the adder 22 via a line 23. The adder serially adds the contents of the shift registers 18 and 26 and shifts the sum obtained back into the shift register 26 via a line 28. The contents of the shift register 26 are then transferred to a second counter 50 on the "down" input of the second counter 30, 32 counting pulses are counted in at a fixed counting frequency by a counting pulse line. As a result, the second counter 30 is counted empty. A bistable multivibrator 34 is set at the beginning of the empty counting and is reset again by the empty counting signal when the second counter 30 is set to zero. The bistable multivibrator 34 controls a controlled electronic switch i in the form of a field effect transistor 38 via a line 36, via which a voltage U _Q + is applied to the input of an integrator 40. The output voltage of the integrator 40 is applied to the input of the analog-digital converter 12 as a correction voltage. This reduces the effective input signal of the analog-digital converter.

In a second zeroing cycle, the counter 14 is loaded with the digital equivalent of the decreased signal. This new actual value, which in the second gauze adjustment cycle with I ₉ or

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should generally be designated by I in the η th zero adjustment cycle, the adder 22 _{adds to the content X 2} or χ of the second shift register 26. The sum obtained is read into the shift register 26 again. At the end of the η th Hull adjustment cycle, the number is thus in the shift register 26

^x n + 1 = ^x n + V

This number is transferred to the second counter 30, and by counting this counter empty, the flip-flop 34 for a proportional time is set and the voltage across the field effect transistor 38 to the integrator - previously reset to STuIl 40 switched.

The values I converge to zero, so that after a Series of full adjustment cycles of the output of the analog-to-digital converter 12 is zero '.

In FIG. 2, the first counter 14 is a binary counter with three counter stages of four bits each. The counter stages of the counter 14 are parallel.mit three corresponding stages of the shift register 18 are connected. The shift register is "loaded" via a line 42, i.e. the reading of counter 14 is taken over. In the counters, pulses are sent via a line 44 from the analog-to-digital converter 12 counted.

Shift clock pulses from a line 46 .die in the shift register 18 stored information over a line 48 to an input 50 of a conventional adder 52. The output of the shift register is connected to the second input 52 of the adder via a line 54 26. Clock pulses are also sent to the shift register 26 via a line 56 in synchronism with the clock pulses on the line 46 given. The numbers stored in shift registers 18 and 26 are added by adder 22 and via line 28

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read into the shift register 26 again.

The adder contains an exclusive OR gate in a known manner, one input of which is connected to the input 50 of the adder 22. The second input of the exclusive OR gate 58 is connected via a line 60 to the output of a flip-flop 62. The output of the exclusive OR element 58 is connected to an input of an exclusive OR element 64. The other input of exclusive-OR gate 64 is connected to the second input 52 of the adder 22 _O the output of the exclusive OR gate 64 is applied to the set input of a bistable multivibrator 66. The output of flip-flop 66 is located on the output line 28 of the adder, the output of the exclusive OR gate is at one input of a NAND gate, the other input of which is connected to the second input 52 of the adder. The output of the FAID gate 68 is connected to an input of a NAND gate 70. Another NAND gate 72 is connected to an input at the input 50 of the adder 22 _O The other input of the NAND gate 72 is located on the line 60 from the output of flip-flop 62. Via a line 72 are the clock inputs of flip-flops 62 and 66 as well as the clock inputs of the shift register acted upon by the clock signal. The bistable flip-flops 62 and 66 can be reset via a line 76 at the beginning of the addition _e

In the bistable multivibrator 66, the sum of the bits occurring at the inputs 50 and 52 is formed and stored in the usual manner, while the carry is stored in the bistable multivibrator 62. The known mode of operation of the circuit will be explained using an example. The binary numbers OL and LL are to be added. Before the arithmetic operation, the two flip-flops 62 and 66 are reset. The output of the bistable multivibrator 62 is thus 0. It is thus at the input of the exclusive OR element 58 L ¹ via input 50 and 0 via line 60,

509819/0939 * " ¹² "

The output is therefore I. Both inputs L of the exclusive-OR element 64 are present, namely one from the output of the exclusive-OR element 58 and the other from the second input 52 of the adder 22. The output of the exclusive-OR element 64 is therefore O. Accordingly, the bistable multivibrator 66 remains in its reset state and outputs the output signal O to the output line 28. At one input of the BAIO element 68 is I from the output of the exclusive OR element 58. At the other input of the NAHD element 68 is L from input 52 of adder 22. The output of the SAED element 68 is therefore 0. L from the input 50 of the adder 22 is present at an input of the NAND element 72. At the other input of the NAHD-G element 72, O from the output of the bistable multivibrator 62 is present. The output of the NAND element 72 is therefore L. At the inputs of the IAID element 70 there is therefore one 0 and one L, so that the output sends the signal Ii to the preparatory input of the bistable multivibrator 62. The clock pulse on line 74 therefore appears at the output of the bistable trigger circuit 62 and on line 60 therefore appears for the addition of the next digit at the output of the bistable trigger circuit 62 and on line 60 the carry L. From the shift register 14 appears at the next digit at the input 50 the signal 0 and from the shift register 26 the signal L _{9 appears at the input 72}

At the input of the exclusive OR & element 58, 1 appears once from input 50 and once I from line 60 (carry over from the previous addition). The output of the exclusive OR element is therefore O. This output is at an input of the exclusive OR element 64. The second input of the exclusive OR element 64 receives the signal 0 via the input 52 of the adder 22 of the exclusive OEEE-rG-liedes 64 is therefore 0, and this signal is given to the preparation input of the bistable multivibrator. At the input of the NAND element 68 there is 0 from the output of the exclusive OR element 58 and 0 from the input 52. The output is therefore I _0. I vom is present at one input of the NAND gate 72

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Input 50 of adder 22, and the other input is L Sound line 60 »The output of the HAHD-G song 72 is therefore O, so the output of the KAED element is 60 L, and accordingly is also the carry output for adding the next digit »

The sum formed by the adder 22 is read serially into the shift register 26 and, in the event of a pulse on a line 78, is transferred to the binary counter 30, which consists of four counting stages with four bits each. Hit the takeover pulse on line 78, the bistable flip-flop 34 is set at the same time _o A clock frequency is paid into the down input 80 of the counter 30 via line 32. This frequency is supplied by an oscillator 82 of about 3 ₉ 2 MHz and via a frequency divider 84 on the line 32 given »This means that the counter 30 is" empty.ergezah.lt "<> The empty counting pulse of the counter 30 resets the bistable multivibrator via input 86 to ₀

In the set state, the bistable multivibrator 34 controls the field effect transistor 38 at the input of the integrator via line 36 4Oo

By a field effect transistor 88, the integrator 4O _5, which may be designed as a conventional analog Miller integrator is _p reset by a pulse on line 89 in each case prior to the setting of flip-flop 34 _o

Taking advantage of some of the same components, the device is further designed such that a Siehung can be carried out, i.e., "ho s that a predetermined analog signal a predetermined digital output can be assigned _o For this purpose a further shift register 90 is provided" In this shift register 90 the counter reading of the counter 14 can be read in

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B input of the analog-digital converter 12 is connected, brought to the desired value _o This value is then transferred to the shift register 90 »The series output of the shift register is fed back to the series input of the same. In addition, it is connected to the middle contact of a switch 92 shown in this way in FIG. 1.

Another shift register 94 has its series input via a line 96 at the output of the adder 22. The series output of the shift register 94 is via a line 98 with the in Pig. 1 lower contact of switch 92 connected ,, the top one Contact of switch 92 in Fig. 1 is connected to the series output of shift register 26. The movable contact arm of the Switch 92 is connected to an input of adder 22.

The content of the shift register 94 can be transferred to a counter 100. The "down" input of the counter 100 is acted upon by a counting frequency; and reset by the empty signal of the counter 100 ₀ The bistable flip-flop 102 controls two electronic switches in the form of the field effect transistors 106 and 108 via a line 104, of which the eraterer is on the let signals input 10 and the latter in series with the output of the integrator 4-0, i.e. with the correction signal, is switched.

The mode of operation of the arrangement described is as follows?

As described, the setpoint value is stored in the shift register 90. An Ileßsignal is now input to the Hess signals created, which is to be displayed digitally with the predetermined display stored in the shift register 90 »In the binary counter H is thus the actual value I, while in the shift register 90 the

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Setpoint S is stored. The actual value I is in the shift register 18 transferred. The switch 92 is first switched to its middle position. The series outputs are then used of the shift register 18 and the shift register 90, the actual value and setpoint value are fed to the adder 22, which now acts as a subtracter, at its output a number corresponding to the difference ^ = S - I is formed and via line 28 into the serial input of the Shift register 18 is read.

In the second part of each calibration cycle, the switch 92 is switched to its lowest position. The content of the shift register 94 together with the difference stored in the shift register 18 is now applied to the inputs of the adder 22 (or subtracter). The output of the subtracter 22 is sent via line 96 to the series input of the shift register 94.If Y _{n is} the content of the shift register 94 at the end of the η-th adjustment cycle, then the content of the shift register 94 is at the end of the n + 1 (-th) adjustment cycle

^X n ₊ 1 = ^Y n. ~ ⁴

The contents of the shift register 94 can be used at the beginning of the alignment process be chosen so that the bistable multivibrator 102 controls the field effect transistors 106 and 108 for the full period. This through-control time is increased by one each from adjustment cycle to adjustment cycle by the above algorithm the amount corresponding to the difference between the nominal value and the actual value is reduced, these differences becoming increasingly smaller, so that a convergence of the display or the digital output in the counter H takes place against the desired value.

In FIG. 2, the shift register 90 is formed by three stages of four bits each, which are connected in parallel to the outputs of the counter H are. The content of the counter H is indicated by a signal

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Line 42 via line 110 and a UUD-G song 112 taken over, if A hand-operated switch 114 sends an L signal to the second input of the ΙΠΠ) element 112. Via line 116 the shift register receives 90 clock pulses from line 46 via a TMD element 118, which is controlled via a control line 120, via which the operating mode is switched to "calibration mode".

In calibration mode, the output of the shift register 90 is via a Line 122 and a UliD element 124 at "input 52" of adder 22. Via a control line 126 there is also an input of an exclusive ODEH element 128, which is connected between the input 52 of the Adder 22 and the HAHD-G-Iied 68 is switched on, L signal, whereby the adder is switched to subtraction »The control line 126 receives an L signal via an OR element 128, on which there is a line 130 which, when switching to "calibration mode" = ' L signal leads and on the other hand a line 132, on which L signal with negative sign of the input signal to analog-digital converter 12 is given so the output of adder 22 is over line 134 connected to the shift register 94, whose series output via line 98 to an input of a UD element 134 is present. The second input of the UKD-Glie & es 134 is with the control line 130 connected via line I36 «The output of the UHD element 134 is connected to input 52 of adder 22. A UIlD link 138 is in the junction between line 54 from the shift register 26 to the adder 22 and is supplied by a control line I40 masters, which receives an L signal in "Uullabgleichbetrieb". The shift register 94 receives clock pulses via a line 142 and a UiJD gate I44 from line 46. The second input of the UHD element 144 is connected to control line 36. After discontinuation of the signal on the control line 36 remains the content of the Shift register 94 stored in this and can during the subsequent measuring process by a transfer signal on a

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Line 146 can be taken over into the counter 100 again. The takeover signal on the line 146 sets the bistable multivibrator 102, which is reset by the empty counting signal at the output of the counter 100 after it has been counted empty _e

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Claims (1)

Claims Device for adjusting the digital display of an analog signal, containing an analog-digital converter with signal integrating Means and a counter in which the digital output of the analog-digital detector appears, as well as a analog signal input influencing this output, in which a controlled electronic switch is located with a pulse duty factor determined during at least one adjustment cycle is controllable, marked by / a) Kittel for adding a number (18, 22 or 18, 90, 22) that corresponds to the deviation of the respective counter content of the said (first) counter (14) of a desired value corresponds to the content of a (first) shift register (26 or-, 94), b) a second counter (30 or _o 100) first in the so modified content of said () shift register (26 resp. "94) is pulse be read by an acquisition and the" down "input zuia with a counting frequency 'empty counting the Counter (30 or 100) is applied, and c) a bistable multivibrator (34 or 102), which by the takeover signal can be set and by an empty counting signal can be reset when the counter is empty and through which said electronic switch (88 106, 108) is controllable » - 19 - 509819/0939 Device nach.-Claim 1, characterized in that for automatic zero point correction, the "said" means for adding "have a second shift register (18) in which at the beginning of each calibration cycle "with an empty signal on one Measurement signal input of the analog-digital converter (12) the content of the first counter (H) can be read, as well as an adder (22), at whose inputs (52, 50) the series outputs of the first "or the second shift register (22" or. 18) are present and whose output is connected to the series input of the first shift register (26), and that via the controlled electronic switch (38) a constant voltage can be applied to an integrator (40), the output of which is an analog 'Measurement signal forms an overlaid analog correction signal. Apparatus according to claim 1 or 2 for comparing the digital Display of an analog signal, such that a given analog input signal of a given finite digital Display corresponds to, marked by a) a shift register (18) in which the counter content can be transferred at the beginning of each calibration cycle, b) a shift register $ 90) with one on its serial input returned series output, into which said predetermined digital display can be read in parallel is, c) a connected for serial subtraction Adder (22), the inputs of which are connected to the series outputs of the two shift registers (18, 90) and whose output is connected to the serial input of a shift register (18), - 20 - 509819/0 939 d) a shift register (94), the series input of which is connected to the output of an adder (22), the two inputs of the adder (22) being connected to the series outputs of the two last-mentioned shift registers (18, 94) and the content of the last-mentioned shift register (94) can be read into a counter (100) that can be counted empty, by means of which a bistable multivibrator (102) for controlling the electronic switch (106, 108) is set and reset, _{or the like} 4. "The device according to claim 3, characterized in that a single adder (22) is provided and de.B by a switching device (92) which during a first part of each adjustment cycle in a first switching state and during a second part of the adjustment cycle in a second switching state can be switched, one input of the adder (22) ± i \ i first switching state of the switching device (92) with the series output of the shift register (90) storing said predetermined digital display and in the second switching state with the series output of the shift register (94) is connected, the content of which can be read into the empty counter (100) " 5ο device according to claim 4, characterized in that in a single shift register (18) whose series input.ga.ng with the Output of the adder (22) and its series output and the other input of the adder (22) is connected, once the Count of the counter (H) forming the output of the analog-digital converter (12) can be read in in parallel and then that of the difference between this counter reading and said predetermined one digital display corresponding number is read in serially from the output of the adder (22) » - 21 - 509819/0939 BATH ORIGINAL Device according to the claims. 1 "to 5,. This means that a single output device (22) is provided for zero adjustment and calibration, desuen an input into a: a third switching state of the switching device (92) with the series output of the first shift register (26) of the adjustment device and whose output is connected to the series input of this shift register (26) _o 5098 19/0939 BATH ORIGINAL