DE1548794A1 - Method and circuit arrangement for triggering an integrator - Google Patents

Description

The invention relates to a method for triggering the operation of an integration circuit for integrating an electrical signal and a circuit arrangement for performing "execution of this method" The triggering of an integrator must be known for the duration * df occurrence of the signal to be integrated trfolftn ".

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BATH ORIGINAL

by measuring the surface of the signal, I wish to obtain a high level of accuracy for the dosage of a component. but so far i ^ö "to t in the current state d ^ r Nicut technique capable of such integrators at a particular wiederholbaren- 8 to.i Ie trigger of the signal to be integrated and n ± e i..n a given location on uignalende to stop,

The invention is based on the object of creating a method of the type mentioned at the outset, di.v. avoid the aforementioned deficiencies liiatit. In the method proposed here, this is achieved above all in that, according to the invention, the level of the 8ϊ., Η ·.. Any successive measurements made in this way are compared, every difference between two successive measurement results is displayed and this difference is used to control the integration process. According to the invention, the method for triggering an integrator consists in that;} every change in the input level of any signal is displayed: - and the pulses that result from the comparison of the level reductions taking place in any way, for the control device Integration process can be used, Xn the following description of the method according to the invention, for example, attention is paid to the processing of signals in the munerie and analog: - ui Syeteeen »". "-.- ■; .-. "'■"; - .:;' . : '.'- ■'. · - -. "■ -.- _: ·.

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In a first embodiment of the method according to the invention. For the numerical processing of signals, the integrating signal is converted into pulses with the size of the signal of proportional frequency and the number of these pulses is stored over successive equal time segments by entering them alternately in two pulse counters, see above Then the pulse numbers determined by two successive counts are compared with each other, every positive or negative deviation between the two pulse numbers is displayed and this deviation is used to control the integrator depending on its size.

In a further embodiment of the method for numerical Processing of signals, the signal to be integrated is converted into pulses with its size "proportional frequency" transformed and the number of see over a given period of time The setting impulses are entered into two counters at the same time, then these counters will appear at each time period reset to zero while the number of Im « pulse 'is fed to a memory, furthermore in the second counter the complement of the number contained in this memory ■ - = .- ■ -, - .. ". ^ - & i> :; a »= -: · ■■■. · .; ' ■■ ·. · ■ '.. "■■ - .. _ < . .. ■ ■ "" ... ■ - ". .--. ■ - ■ Pulses introduced and during the subsequent period the number of pulses corresponding to the Y / ert of the signal to be integrated entered simultaneously in both meters, of which the

the second is already partially filled, and finally the loading; drive of the integrator is auageiöst ^ when the second counter A capacity is crossed as a function of the threshold values is selected from which the signal is to be integrated *

BATH ORIGINAL

According to a third embodiment of the method for Analog processing of signals is carried out alternately in two integrating circuits during successive equal periods of time the fourth of the input signal to be integrated is restored and any between two consecutive ones Representations of the value of the au integrating signal appearing positive or negative difference displayed and dependent the value of which is controlled by the operation of the integrator.

According to a fourth embodiment of the inventive Method for analog processing "of signals is the Changes in the voltage of the signals to be integrated are measured corresponding to the differential voltage and to control the operation: abs of the integrator utilizes the fact that the absolute value this differential voltage exceeds a controllable threshold value »

The invention also relates to a circuit arrangement for carrying out the method proposed here. This circuit primarily has circuit elements which periodically and over the same time period measure the level of the signal to be integrated, compare two successive measurements of this signal, any positive or negative deviation between them display both measurements and apply the resulting impulse to the control of the integrator. Integration only during the eventual occurrence "tee signals and taxes"

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In the case of digital processing of signals preferably circuit elements are provided in order to alternately perform the 'counting the pulses to reset the various counters to Hull, and an associated an overflow counter-flop before further overflow of this counter in the idle state zürückzuversetzen _e

The circuit arrangement straight? the invention allows especially to indicate any change in the level of the signal and the impulses resulting from the comparison to the control of the integration process. In the case of the numerical processing of signals, circuit means are advantageously provided to reset the two Counter, the transfer of the number of pulses of the first counter into a memory and the transfer of the complement of that in this The number of pulses contained in the memory is transferred from the memory to the to synchronize the second counter and da3 the second counter reset the assigned overflow toggle link to the idle state before the subsequent overflow »

Further details of this circuit arrangement and through

the advantages achieved are evident from the description below

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the drawing shows the / Sonaltungsanrichtungen the invention proposed type in four exemplary selected embodiments each in the block diagram schematically illustrate ju_-32s

Pig 1 shows a first embodiment of a circuit according to FIG

Invention for Numerical Processing of Signals, 909838/0685

iOBlGlNAU J.,, ■ *., ... ■

2 shows a first embodiment of the circuit according to the invention for the analog processing of signals,

3 shows a second embodiment of a circuit according to FIG Invention for the numerical processing of signals and

4 shows a second embodiment of the circuit according to the invention for the * analog processing of signals _e

In the circuit of FIG. 1, a voltage source 1 feeds a voltage-frequency converter 2, which is connected on the one hand to a current gate 3 and on the other hand to a further current gate 4 and finally is connected to a third power gate 11. The outputs of the Electricity gates 3 and 4 are connected to two counters 5 and G, which are each connected to the input of an overflow counter 7. The two Outputs of a trigger circuit 8 are at the inputs of the Electricity gates 3 and 4 »Finally, a timer 9 is with the entrance of the tilting circuit 8 and a v / pus, also at the overflow counter 7 connected flip-flop 10, the output of which is at the power gate 11 »

In the circuit of the FIg ₀ 2, a voltage source 1 'feeds a voltage-frequency converter 2 ^f , which is connected on the one hand to a current port 3 ^f i on the other hand to a further current port 4 * and finally to a third current port 12'. The output of the current gate 3 ^f is connected to an integration ^{element which comprises a capacitance 5 1} and a resistor 6 · and is connected to the input of a symmetrical differential ^{amplifier 9 1} , while the output of the current gate 4 ^{1 is connected} to a further integration ·

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element is connected, which consists of a capacitance 7 ¹ and a Y / i · * · derst-nd 8 ^l and is connected to the other input of the differential ^{amplifier 9 1} . The two outputs of Verstär · kers 9 'lie at the Stronrtoren 10' and 11 ^f _f whose Auegänge are connected together and control the stream gate 12 '. A time "" work 15 'ultimately controls the state of a flip-flop 14 ¹ "whose outputs are connected to the inputs of the two current gates 3 ¹ and 4'.

The operation of these two circuits described above is as follows: In the case of the numerical processing of signals (3? steered to one or the other of the two power gates 3 and 4 according to the state of the tilting circles 8 controlled by the timer 9. During a given period of time the pulses are counted in the counter 5 , then at the end of this period of time the trigger circuit 8 changes its state, and the pulses are then counted in the counter 6 during the following, the same period of time. The difference between these two pulse counts, whether poeitiy or whether negative, is used by the ', I ' overflow counter 7 of the given capacity. When 8-wan ^'1 J. wirfl not filled, resulting calibration simply a deviation of E ij * - gangßßignale, and it turns verifiable no overflow pulse of EahlerB but ay when the capacity dee counter 7 Exceeded _f results in a ÜberlaufifflSKi »» of the! state läeet change 10 of the Kippgliedee _v the Stroator the Ή Opens and integration

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BATH ORIGINAL

of the signal during the period of its growth as well as allows during the period of its falling. The timer 11 resets the various counters to Hull and also performs the toggle 10 before each renewed overflow of the counter 7 in returns to the idle state, so that when the signal ceases, the counter 7 no longer emits any overflow pulses and the flip-flop 10 remains in the idle state and thus locks the power gate 11 »

In the case of the analog processing of signals (FIG. 2), the voltage source 1 'supplies a signal which is converted into a corresponding frequency ^{by the voltage-frequency converter 2f.} The pulses emitted by the converter 2 'are directed to one or the other of the two current gates 3 ¹ and 4' ^{according to the state of the 7} ^ PPgIi ede s 14 ^{f controlled by the timer 13 '} Integration element 5 ', 6' is converted into a voltage equal to the voltage of the input signal of the integrator, then at the end of this time segment the flip-flop 14 'changes its state, and the pulses are then transmitted during the following, the previous same time segment by the integration element 7', 8 ^{f converted} into a voltage equal to that of the input signal of the integrator. The difference between these two voltages thus restored is applied to the differential amplifier 9 ¹ . If the signal increases by a sufficient value, the positive threshold value trigger 10 * delivers a pulse which controls the opening of the current gate 12 '. When the signal reaches its maximum value and begins to drop, the positive threshold value trigger 10 closes ^!

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, again da8 Stromtor 12 'and the negative threshold value trigger 11' opens this same stream gate 12 'again, which thus the coding while the signal is falling. The cessation of the signal leads to the closing of the current gate 12 'by the negative threshold value trigger 11' and the two threshold value triggers 10 * and 11 'are then in the idle state and block the power gate 12 * · l / enn the change in the signal is not sufficient to achieve one of the to trigger both threshold value triggers, there is simply a derivation of the signal and the integration is not carried out «

In the circuit arrangement of FIG _o 3 a tension "feed voltage source 21 a voltage-to-frequency A / andler 22, which is connected on one side to a stream gate 30, on the other hand, to a first counter 23 and a second, so-called counter-counter 25 _e The two counters 23 and 25 are connected to one another via a memory 24. The counter-counter 25 is connected on the one hand to a flip-flop 27 and on the other hand to a decoder 26. The flip-flop circuit 27 controls a first stream gate 32 and a further stream gate 30 The output of the current gate is connected to an input of the current gate 30 which, in the open state, transmits the pulse coming from the converter 22 to the integrator. A flip-flop circuit 31 is connected to the counter 23 and memory 24.

When the Pig 4 is switched, an energy source 21 feeds it

parallel to each other a voltage I frequency wY / aiidler 22 * and a

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BAD ORJGiNAL

Differentiating element, which is composed of the capacitance 23 'and a resistor 24' . The output of this differentiating element is connected to two thresholds connected in parallel. value triggers 25 * and 26 ¹ , which are connected to a current gate 27 ¹ or «28 'o The output of the converter 22' is at the input of the two current gates 27 'and" 28 ^f , which have a single output "

The mode of operation of the two circuits just described is as follows: In the case of the numerical processing of signals (FIG. 3), the voltage source 21 supplies a signal which is converted into a corresponding frequency by the voltage-frequency converter 22 and the pulses are converted Counted in counter 23, also in counter counter 25 and transferred to the memory. Counter 23 and counter counter 25 are reset to zero for a given period of time, so that a complementary number of the number of pulses transmitted to memory 24 is sent to counter counter 25 transmitted, these processes being synchronized by a timer "In the subsequent counting period -" the pulses reach the counter Zj and counter-counter 25 and lead the latter to its maximum capacity if the number of pulses is the same during the previous counting period »If this number of pulses is smaller, ie if the signal has decreased, there is no overflow of the Ge counter 25 more. When the number of pulses increases, the counter-counter 25 overflows, and the overflow pulse changes the state of the Xippkreiaes 27, which opens the electricity gate 30

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6AO ORIGINAL

and allows the slack of the andler 22 transferred from the Y / "pulses, Y / hen tilting of the counter 25 has occurred, can this re-fill" Me he na to a predetermined value surrender, there is a decoding this number, that a pulse was set at the output of the decoder 26. The pulse changes the state of the flip-flop 28, which together rait. the flip-flop 27 causes the current gate 29 to open, which has the effect that the state of the flip-flop circuit 31 changes, which thus halts the transmission of the contents of the counter 23 to the memory 24, the timer sets - as already indicated cyclically the whole the counter back to zero, at the additional outputs of the flip-flops 27 and 28 there is a current gate 32c. In the event of the presence of a signal, this current gate is open

In the case of analog signals on treatment * (Fig _{4: 0)} provides the voltage source 21 ', a signal dui'ch the voltage-to-frequency converter 22' are converted into corresponding frequency and / jlüichzeitif? by which the circuit is differentiated from the capacitance 23 'and the resistor 24', the differentiated voltage due to the voltage change in the signal is given to the two threshold value triggers 25 'and 26', of which the erolerc has a positive threshold value and the second has a negative threshold value, If the rise in the voltage of the signal is sufficient, the positive threshold value trigger 25 * opens the current gate 27 ', which thus allows the wall-

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ler 22 ^f coming pulses reach the integrator. As long as the signal is growing, the threshold value trigger 25 'reads the coding of the signal when the latter reaches its maximum and begins to fall, the current gate 27'ι closes and then the negative threshold value trigger 26 * opens the current gate 28 ¹ as soon as the voltage drops of the signal is sufficient, as a result of which the pulses coming from the landler 22 * can reach the integrator. When the signal stops, the negative threshold value trigger closes the current gate 28 ¹ , and the two current gates 27 'and 28 are then in their blocking state simply derive the signal and the integration is not carried out

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Claims (1)

~ 15 Claims j ο Method for triggering the operation of an integration circuit for integrating an electrical signal, characterized in that the level of the signal to be integrated is periodically measured over given, short periods of time compared to the duration of the signal to be integrated, the results of two successive measurements made in this way are compared , every difference between two successive measurement results is displayed and this difference is used to control the integration process » 2β method according to claim 1, characterized in that the Signal to be integrated converted into pulses with the size of the signal proportional frequency and over successive the number of these pulses is stored in two pulse counters by entering them alternately in the same time periods then the pulse numbers determined by two successive counts are compared with each other. any positive or negative deviation between the two pulse numbers is displayed and this deviation is used to to control the integrator depending on its size * 3. The method according to claim 1, characterized in that the dadurah signal to be integrated into pulses with its size more proportional Converted to frequency and the number of turns over a 909838/0685 " _um BATH ORIGINAL given time segment adjusting pulses simultaneously is entered into two counters, then at least every time period these counters are reset to zero while the number of pulses entered is fed to a memory is also introduced into the second counter the complement of the number of pulses contained in this memory and during the following period of time the v / ert number of pulses corresponding to the signal to be integrated is entered in both meters, of which the second is already partially full, and finally the operation of the integrator is triggered when the second counter exceeds its capacity, which depends on the Schwellv / erts is selected from which the signal is to be integrated, 4 «Method according to claim, characterized in that during successive equal periods of time alternately in two integrating circuits the value of the input signal to be integrated is restored and any between two successive representations of the value ow to be integrated The positive or negative difference occurring in the signal is displayed and, depending on its value, the operation of the Integrator is controlled " 5. The method according to claim 1, characterized in that the the changes in the voltage of the signal to be integrated appropriate differential voltage measured and used for stunt; run,.-: of the operation of the integrator utilizes the fact '' ircl, 909838/0685 - 15 - 8AD ORJGlNAt • that the absolute value of this differential voltage is controllable Exceeds threshold c 6. Circuit arrangement for performing the method according to claims 1 and 2, characterized by a voltage-frequency converter (2) controlled by the signal to be integrated, which is connected on the one hand to a current gate (11) on the integrator and on the other hand to two of one through a Timing mechanism (9) actuated toggle element (B) alternately open and closed current gates (3, 4) are connected, each of which is followed by a counter (5, 6), at the outputs of which a record the difference in the numbers contained in them overflow counter (7), which in the case of the overflow can open the stream gate located at the integrator (11) (Figure 1 _e) · Circuit arrangement for carrying out the method according to claims 1 and 3, characterized by a voltage-frequency converter (22) controlled by the signal to be integrated, the two counters [z'-j, 25) connected by a memory (24) are connected, furthermore by a circuit which periodically "resets the two counters and the memory to zero, the result of the first counter (23) in the memory (24) and the complement of the number of pulses counted in the two-tone counter (25), as well as through a circuit (26 to 2Q) influenced by its overflow, which opens a current gate (3 <>) that sends the pulses from the voltage-frequency converter (Z2) to the Integrator arrive läast (Fi ^.,), 909838/0685 BAD ORiGiNAL 8 _β circuit arrangement for carrying out the method according to claims 1 and 4 »characterized by a voltage-frequency converter (2 *) i controlled by the signal to be integrated, at its output a current port (12 ·) connected upstream of the integrator and two further current ports (3 ^f , 4 ¹ ) are connected, the opening of which is controlled alternately in regular time segments by a timer (13 ¹ ) and a flip-flop element (14 ¹ ) and which are each connected upstream of an integration element (5 '* i 6 * i 7% 8 ¹⁾ , which restores a voltage equal to the voltage of the signal to be integrated, and through a circuit (9 ¹ ) »which forms the difference between these two thus restored voltages, and an amplifier (9 ¹ )» 4 amplifies these differences and opens the Voltage-frequency converter (2 ') with the integrator connecting current gate (12 ») controls (Fig. 2). Circuit arrangement for carrying out the method according to claims 1 and 5, characterized by the voltage-frequency converter (22 *) controlled by the signal to be integrated »at the output of which two current gates (27 ¹ , 28») connected upstream of the integrator are simultaneously connected, by one connected in parallel to the Y / andler (22 *), made of capacitance (23 *) and resistor (24 ') formed a circuit that simultaneously determines the differential voltage of the signal to be integrated to a trigger (25 *) with a positive threshold value and a trigger (26 «) with a negative threshold value, from 909838/0685 - 17 - each of which controls one of the two power gates (27, 28 *), which come from the voltage-frequency converter (22 *) Let impulses reach the integrator (Pig «4) β 9 0 9 8 38/0685 _BAD