CH617510A5 - - Google Patents

Description

The invention relates to a measuring amplifier with a digital output, consisting of a preamplifier with a switchable gain and an analog-digital converter, and is characterized in that an integrating amplifier with stepwise switchable integration times is switched on between the preamplifier and the A / D converter.

The invention is explained in more detail below on the basis of an exemplary embodiment shown in the drawing. Show it:

Fig. 1 is a block diagram of a measuring amplifier according to the invention and

Fig. 2 pulse diagrams for functional explanation.

1 essentially consists of a preamplifier 1, an integrating amplifier 11, a comparator 20, an integrating time control logic 12 and an analog-digital converter 22. The digital output signals of the measuring amplifier are a microprocessor designated | iC fed for further processing.

The preamplifier contains an operational amplifier 1 a, which is connected to resistors 2, 3, 4, 5 and 6, of which the resistor 6 is fixed to ground, while the resistors 4 and 5 can be connected to ground by means of switches 7 and 8 . The resistors 2, 3, 4, 5 and 6 are dimensioned in such a way that a basic gain v. e.g. 100 mV / [generally gives. If switch 8 alone is closed, the pre-amplification increases by a factor of 23, and if both switches are closed, by a factor of 26. A measuring range preselection stage is used to switch the amplification; 9a is provided, which controls a logic stage 9, which in turn actuates the switches 7 and 8 and generates corresponding logic output signals on lines 10 of the selected amplification. These output signals represent part of the exponents of the digitized measurement signal. The mantissa is generated by the A / D converter. The other part of the exponents is formed by the integrating amplifier.

The integrating amplifier 11 comprises an operational amplifier 17 which is connected to a capacitor 18. The latter is bridged by a switch 16, which is controlled by a switching stage 16a ï. The inverting input of the amplifier is connected to two switches 14 and 15, which are controlled by a switching stage 14a.

The integration time control logic 12 essentially consists of a binary counter and an AND gate as well as various other 20 gates.

The function of the circuit shown in FIG. 1 is described below using the pulse diagrams according to FIG. 2. Line a of FIG. 2 shows the control logic 12 clock pulses (lmsec) supplied via its input 12a.

25th

Line b shows a start pulse, which triggers the measurement process via input 13 of control logic 12. Lines c, d u. e show the switching states of the switches 16, 14 u. 15. Line f) shows the time course of the voltage at the output 19 of the integrating Ki amplifier and the reference voltage at the input 20b of the comparator 20. Line g) shows the logic signal at the output 20c of the comparator 20. Line h) shows time pulses which are generated in the integration time control logic 12 after 4, 8, 16, 32 or 64 ms. Line i) shows the logical output signal of the AND gate contained in the control logic 12. Lines j, k, 1 u. m show the logical signals on lines 23 (exponents). Line n) shows the logic signal at output 21 of the control stage. Line o) shows the logical state at the output 28 (BUSY) of the A / D converter 22 u. thus the 4 »state of the converter itself.

Different, typical phases can be distinguished in the course of the entire measuring process:

Before the time I, the preparation phase, between the times I u. II the zero phase (RESET), between 45 the times II u. III the integration phase, and between times III u. IV the change phase.

A start pulse on input 13 of control stage 12 triggers the following sequence:

The counter contained in the stage is set to zero, so switch 16 is briefly closed and the capacitor 18 is thereby discharged. Simultaneously with the reopening of switch 16, switch 14 is closed and switch 15 is opened and the counter for the clock pulse (line a) is released. At the start of the integration phase, the voltage at output 19 rises steadily with a slope that is proportional to the input signal (line f). After 4.8, 16.32 and 64 ms, the counter generates short pulses (line h) which are compared with the output of the comparator 20 (line g) via the AND gate contained in the control stage 12. As soon as the mi voltage at the output 19 of the integrating amplifier 11 (line f) reaches a reference voltage present at one input of the comparator 20 (line f), a logic 1 (line g) arises at the comparator output, which is indicated by the next time stamp ( in the present example at 8 ms), address the AND gate - <> 5 chen, the integration is terminated and the A / D conversion is started via line 21.

D abei the switch 14 is opened again and the switch 15 closed (lines d, e), the counter from the clock generator

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disconnects and output 21 is set to zero (line n). The latter It would also be conceivable that with the 13th bit via the logic stage for the A / D conversion means the signal with the conversion to 9 (depending on the preamplification) would be reduced automatically. This would have started. However, since the level of the output signal of the integrating amplifier Disadvantage that at least the time for a stronger one depends on the set integration time, forms the whole measuring sequence, or, if the gain reduction in the latter is insufficient for the magnitude of the first 5 steps to be measured, even for two measuring sequences

Signal. The integration time can therefore be considered an exponent.

Exponent representation can be used. That is why the individual is for measurement applications without rigid

Exponents corresponding to integration times are indicated by area preselection, a logical ones with the aid of two further comparators are provided on each of the lines 23 (lines 24 and 25 are used for automatic preselection. In the j-m) - m preparation phase is initially done with medium gain

As soon as the conversion is finished, measured appears at the output 28, i.e. Switch 8 closed, switch 7 open. If the A / D converter 22 again has a logic zero and the micro now has a voltage at the output 27 of the preamplifier

Processor begins on lines 10, 23 and 26 should result in a mantissa which is higher than a suitably chosen and poll exponent. If the voltage at the output reference voltage at the comparator 24, this responds and

19 (line f) has not risen sufficiently within 4 ms (line h), 15 causes switch 7 to close via logic stage 9,

in order to make the comparator 20 respond, the gain reduction is e.g. a factor of 2? to

Integration time extended to 8 ms or 16.32 or 64 ms.

(Line h). At the end of each integration time, the AND gate checks, in the other case if the comparator 20 has responded with a medium gain. In the positive case, output 27 should result in a voltage which is lower than the integration is terminated, and the start signal for the wall 211 a suitably selected reference voltage on the comparator 25,

given (line n). this drops out (log. 0 at the output) and causes the

In the case of very weak signals, logic stage 9 may also open switch 8, which has not yet increased the reference voltage after 64 ms and preamplification by a factor of e.g. 23 results.

the comparator does not respond. In such cases, the start of each new measurement is made via an input

Integration directly through the time pulse 25 9c of logic stage 9 occurring at 64 ms, the preamplification back to medium

(Line h) canceled and changed. Value switched.

If the reference value already after 2 ms or less The other phases run the same way as reached above, this means that the input signal is too large. Described from

of the entire working range of the A / D converter 22, of course, it would also be possible, by attaching the most significant bit output for the actual conversion, not 1 »of 3 or more comparators, the preamplification in 4 or used. In the present case, this output (overflow) has to be varied more stages.

connected to an alarm device AL. If the alarm device responds, the measurement must be repeated with a smaller preamplification.

C.

2 sheets of drawings

Claims (3)

617 510 PATENT CLAIMS 1. Measuring amplifier with digital output, consisting of a preamplifier with a switchable gain and an analog-digital converter, characterized in that an integrating amplifier (11) with stepwise between the preamplifier (1) and the A / D converter (22) switchable integration times is switched on. 2. Measuring amplifier according to claim 1, characterized in that a comparator (20) connected to the integrating amplifier (11) and a control stage (12) cooperating therewith are provided, the latter switching the integration time to the next higher value when the output signal of the integrating amplifier does not exceed a reference signal applied to the comparator within the integration time currently switched on. 3. Measuring amplifier according to claim 1 or 2, characterized in that it generates digital values in floating-point representation at its output, the mantissa of the values being generated by the A / D converter and the exponents by the preamplifier and the integrating amplifier. In photography technology in particular, there is often the task of measuring small and very small currents with the greatest accuracy and displaying them in digital form. A particular problem is the fact that the currents to be measured are not very small, so that they are almost lost in the noise, but also often have a considerable dynamic range. For example, the photo currents that occur in the photoelectric measurement of master copies are in the range from approximately 100pA to approximately 100 (YES, which corresponds to a dynamic range of approximately 106. To increase the processable dynamic range, measuring amplifiers with a switchable gain level and floating point analog-digital converter (DOS 2 460 907) are generally used today. Integrating measuring amplifiers have proven to be useful for processing the smallest signals that are only slightly above the noise level (DAS 2 059 862 and DAS 2 035 232). However, in many cases, these known measures or devices are still not sufficient in practice or are too expensive. To remedy this deficiency is the object of the invention.