DE2342238A1 - Verfahren zur erzeugung elektrisch isolierter durchgangsverbindungen in einer leitenden platte fuer eine elektrische vielplatten-schaltungsanordnung - Google Patents

Verfahren zur erzeugung elektrisch isolierter durchgangsverbindungen in einer leitenden platte fuer eine elektrische vielplatten-schaltungsanordnung

Info

Publication number
DE2342238A1
DE2342238A1 DE19732342238 DE2342238A DE2342238A1 DE 2342238 A1 DE2342238 A1 DE 2342238A1 DE 19732342238 DE19732342238 DE 19732342238 DE 2342238 A DE2342238 A DE 2342238A DE 2342238 A1 DE2342238 A1 DE 2342238A1
Authority
DE
Germany
Prior art keywords
plate
conductor
film
connections
dielectric material
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
DE19732342238
Other languages
German (de)
English (en)
Inventor
Howard Lee Parks
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Bunker Ramo Corp
Original Assignee
Bunker Ramo Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Bunker Ramo Corp filed Critical Bunker Ramo Corp
Publication of DE2342238A1 publication Critical patent/DE2342238A1/de
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/44—Manufacturing insulated metal core circuits or other insulated electrically conductive core circuits
    • H05K3/445—Manufacturing insulated metal core circuits or other insulated electrically conductive core circuits having insulated holes or insulated via connections through the metal core
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/096—Vertically aligned vias, holes or stacked vias
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09745—Recess in conductor, e.g. in pad or in metallic substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09881—Coating only between conductors, i.e. flush with the conductors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/03—Metal processing
    • H05K2203/0323—Working metal substrate or core, e.g. by etching, deforming
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/03—Metal processing
    • H05K2203/0369—Etching selective parts of a metal substrate through part of its thickness, e.g. using etch resist
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/04—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed mechanically, e.g. by punching
    • H05K3/041—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed mechanically, e.g. by punching by using a die for cutting the conductive material
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/107—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by filling grooves in the support with conductive material
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4614—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49126—Assembling bases
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Insulated Metal Substrates For Printed Circuits (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Combinations Of Printed Boards (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Coupling Device And Connection With Printed Circuit (AREA)
DE19732342238 1972-09-05 1973-08-21 Verfahren zur erzeugung elektrisch isolierter durchgangsverbindungen in einer leitenden platte fuer eine elektrische vielplatten-schaltungsanordnung Pending DE2342238A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US00286163A US3813773A (en) 1972-09-05 1972-09-05 Method employing precision stamping for fabricating the wafers of a multiwafer electrical circuit structure

Publications (1)

Publication Number Publication Date
DE2342238A1 true DE2342238A1 (de) 1974-03-21

Family

ID=23097372

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19732342238 Pending DE2342238A1 (de) 1972-09-05 1973-08-21 Verfahren zur erzeugung elektrisch isolierter durchgangsverbindungen in einer leitenden platte fuer eine elektrische vielplatten-schaltungsanordnung

Country Status (11)

Country Link
US (1) US3813773A (OSRAM)
JP (1) JPS5613039B2 (OSRAM)
AU (1) AU472212B2 (OSRAM)
CA (1) CA981809A (OSRAM)
DE (1) DE2342238A1 (OSRAM)
FR (1) FR2198348B1 (OSRAM)
GB (1) GB1443338A (OSRAM)
IT (1) IT993146B (OSRAM)
NL (1) NL7311996A (OSRAM)
SE (1) SE387514B (OSRAM)
ZA (1) ZA735282B (OSRAM)

Families Citing this family (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3918148A (en) * 1974-04-15 1975-11-11 Ibm Integrated circuit chip carrier and method for forming the same
JPS60168751U (ja) * 1984-04-18 1985-11-08 株式会社　国元商会 コンクリ−ト型枠等の取り付け具
US4894706A (en) * 1985-02-14 1990-01-16 Nippon Telegraph And Telephone Corporation Three-dimensional packaging of semiconductor device chips
US4954875A (en) * 1986-07-17 1990-09-04 Laser Dynamics, Inc. Semiconductor wafer array with electrically conductive compliant material
US4897708A (en) * 1986-07-17 1990-01-30 Laser Dynamics, Inc. Semiconductor wafer array
US5201974A (en) * 1990-02-06 1993-04-13 West Frederick A Method and apparatus for making patterned electrically conductive structures
US5045975A (en) * 1987-05-21 1991-09-03 Cray Computer Corporation Three dimensionally interconnected module assembly
US5014419A (en) * 1987-05-21 1991-05-14 Cray Computer Corporation Twisted wire jumper electrical interconnector and method of making
US5112232A (en) * 1987-05-21 1992-05-12 Cray Computer Corporation Twisted wire jumper electrical interconnector
US5184400A (en) * 1987-05-21 1993-02-09 Cray Computer Corporation Method for manufacturing a twisted wire jumper electrical interconnector
US5195237A (en) * 1987-05-21 1993-03-23 Cray Computer Corporation Flying leads for integrated circuits
US5089880A (en) * 1989-06-07 1992-02-18 Amdahl Corporation Pressurized interconnection system for semiconductor chips
JPH0680713B2 (ja) * 1989-10-11 1994-10-12 三菱電機株式会社 ウエハ試験用プローブカードおよびその製造方法
US5071359A (en) * 1990-04-27 1991-12-10 Rogers Corporation Array connector
US5245751A (en) * 1990-04-27 1993-09-21 Circuit Components, Incorporated Array connector
US5229647A (en) * 1991-03-27 1993-07-20 Micron Technology, Inc. High density data storage using stacked wafers
US5270571A (en) * 1991-10-30 1993-12-14 Amdahl Corporation Three-dimensional package for semiconductor devices
US5249355A (en) * 1991-10-31 1993-10-05 Hughes Aircraft Company Method of fabricating a multilayer electrical circuit structure
US5561593A (en) * 1994-01-27 1996-10-01 Vicon Enterprises, Inc. Z-interface-board
JP2891875B2 (ja) * 1994-06-09 1999-05-17 日本電気株式会社 液晶表示装置
US6080596A (en) * 1994-06-23 2000-06-27 Cubic Memory Inc. Method for forming vertical interconnect process for silicon segments with dielectric isolation
US5698895A (en) * 1994-06-23 1997-12-16 Cubic Memory, Inc. Silicon segment programming method and apparatus
US5891761A (en) * 1994-06-23 1999-04-06 Cubic Memory, Inc. Method for forming vertical interconnect process for silicon segments with thermally conductive epoxy preform
US6486528B1 (en) 1994-06-23 2002-11-26 Vertical Circuits, Inc. Silicon segment programming apparatus and three terminal fuse configuration
US6255726B1 (en) 1994-06-23 2001-07-03 Cubic Memory, Inc. Vertical interconnect process for silicon segments with dielectric isolation
US5675180A (en) * 1994-06-23 1997-10-07 Cubic Memory, Inc. Vertical interconnect process for silicon segments
US6124633A (en) * 1994-06-23 2000-09-26 Cubic Memory Vertical interconnect process for silicon segments with thermally conductive epoxy preform
US5657206A (en) * 1994-06-23 1997-08-12 Cubic Memory, Inc. Conductive epoxy flip-chip package and method
DE4435121A1 (de) * 1994-09-30 1996-04-04 Siemens Ag An Datenbus betreibbare tragbare Datenträgeranordnung
US5487218A (en) * 1994-11-21 1996-01-30 International Business Machines Corporation Method for making printed circuit boards with selectivity filled plated through holes
US7247030B2 (en) * 2004-04-05 2007-07-24 Tyco Electronics Corporation Bonded three dimensional laminate structure
US7172926B2 (en) * 2004-04-21 2007-02-06 Advanced Semiconductor Engineering, Inc. Method for manufacturing an adhesive substrate with a die-cavity sidewall
US7473102B2 (en) * 2006-03-31 2009-01-06 International Business Machines Corporation Space transforming land grid array interposers

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2948051A (en) * 1952-09-20 1960-08-09 Eisler Paul Method of manufacturing an electrically conductive winding pattern
US3077658A (en) * 1960-04-11 1963-02-19 Gen Dynamics Corp Method of manufacturing molded module assemblies
US3351816A (en) * 1965-02-04 1967-11-07 Bunker Ramo Planar coaxial circuitry
US3351702A (en) * 1966-02-24 1967-11-07 Bunker Ramo Interconnection means and method of fabrication thereof
US3351953A (en) * 1966-03-10 1967-11-07 Bunker Ramo Interconnection means and method of fabrication thereof
US3499219A (en) * 1967-11-06 1970-03-10 Bunker Ramo Interconnection means and method of fabrication thereof
US3559285A (en) * 1968-01-08 1971-02-02 Jade Corp Method of forming leads for attachment to semi-conductor devices
US3541222A (en) * 1969-01-13 1970-11-17 Bunker Ramo Connector screen for interconnecting adjacent surfaces of laminar circuits and method of making
US3705332A (en) * 1970-06-25 1972-12-05 Howard L Parks Electrical circuit packaging structure and method of fabrication thereof

Also Published As

Publication number Publication date
SE387514B (sv) 1976-09-06
IT993146B (it) 1975-09-30
ZA735282B (en) 1974-07-31
GB1443338A (en) 1976-07-21
FR2198348B1 (OSRAM) 1979-07-20
AU472212B2 (en) 1976-05-20
US3813773A (en) 1974-06-04
NL7311996A (OSRAM) 1974-03-07
CA981809A (en) 1976-01-13
AU5887673A (en) 1975-02-06
JPS4963967A (OSRAM) 1974-06-20
FR2198348A1 (OSRAM) 1974-03-29
JPS5613039B2 (OSRAM) 1981-03-25

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