DE2324006A1 - Verfahren zur herstellung einer mehrschicht-dickfilmschaltung mit leitenden kreuzverbindungen - Google Patents

Verfahren zur herstellung einer mehrschicht-dickfilmschaltung mit leitenden kreuzverbindungen

Info

Publication number
DE2324006A1
DE2324006A1 DE19732324006 DE2324006A DE2324006A1 DE 2324006 A1 DE2324006 A1 DE 2324006A1 DE 19732324006 DE19732324006 DE 19732324006 DE 2324006 A DE2324006 A DE 2324006A DE 2324006 A1 DE2324006 A1 DE 2324006A1
Authority
DE
Germany
Prior art keywords
circuit
thick film
layers
connections
conductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
DE19732324006
Other languages
German (de)
English (en)
Inventor
Olaf Dipl Ing Sternbeck
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Telefonaktiebolaget LM Ericsson AB
Original Assignee
Telefonaktiebolaget LM Ericsson AB
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Telefonaktiebolaget LM Ericsson AB filed Critical Telefonaktiebolaget LM Ericsson AB
Publication of DE2324006A1 publication Critical patent/DE2324006A1/de
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0017—Etching of the substrate by chemical or physical means
    • H05K3/0026—Etching of the substrate by chemical or physical means by laser ablation
    • H05K3/0029—Etching of the substrate by chemical or physical means by laser ablation of inorganic insulating material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/702—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof of thick-or thin-film circuits or parts thereof
    • H01L21/705—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof of thick-or thin-film circuits or parts thereof of thick-film circuits or parts thereof
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0286—Programmable, customizable or modifiable circuits
    • H05K1/0287—Programmable, customizable or modifiable circuits having an universal lay-out, e.g. pad or land grid patterns or mesh patterns
    • H05K1/0289—Programmable, customizable or modifiable circuits having an universal lay-out, e.g. pad or land grid patterns or mesh patterns having a matrix lay-out, i.e. having selectively interconnectable sets of X-conductors and Y-conductors in different planes
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4664—Adding a circuit layer by thick film methods, e.g. printing techniques or by other techniques for making conductive patterns by using pastes, inks or powders

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Optics & Photonics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
DE19732324006 1972-05-18 1973-05-10 Verfahren zur herstellung einer mehrschicht-dickfilmschaltung mit leitenden kreuzverbindungen Pending DE2324006A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
SE651572 1972-05-18

Publications (1)

Publication Number Publication Date
DE2324006A1 true DE2324006A1 (de) 1973-12-06

Family

ID=20268883

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19732324006 Pending DE2324006A1 (de) 1972-05-18 1973-05-10 Verfahren zur herstellung einer mehrschicht-dickfilmschaltung mit leitenden kreuzverbindungen

Country Status (3)

Country Link
DE (1) DE2324006A1 (US07935154-20110503-C00018.png)
FR (1) FR2184977B1 (US07935154-20110503-C00018.png)
GB (1) GB1425373A (US07935154-20110503-C00018.png)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4258468A (en) * 1978-12-14 1981-03-31 Western Electric Company, Inc. Forming vias through multilayer circuit boards
US4764644A (en) * 1985-09-30 1988-08-16 Microelectronics Center Of North Carolina Microelectronics apparatus
US4667404A (en) * 1985-09-30 1987-05-26 Microelectronics Center Of North Carolina Method of interconnecting wiring planes

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
BE631489A (US07935154-20110503-C00018.png) * 1962-04-27
US3561110A (en) * 1967-08-31 1971-02-09 Ibm Method of making connections and conductive paths

Also Published As

Publication number Publication date
FR2184977A1 (US07935154-20110503-C00018.png) 1973-12-28
FR2184977B1 (US07935154-20110503-C00018.png) 1977-02-11
AU5523573A (en) 1974-11-07
GB1425373A (en) 1976-02-18

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Legal Events

Date Code Title Description
OHJ Non-payment of the annual fee