DE2300853A1 - Rechenmaschine, die in zwei teile aufgeteilt ist - Google Patents

Rechenmaschine, die in zwei teile aufgeteilt ist

Info

Publication number
DE2300853A1
DE2300853A1 DE19732300853 DE2300853A DE2300853A1 DE 2300853 A1 DE2300853 A1 DE 2300853A1 DE 19732300853 DE19732300853 DE 19732300853 DE 2300853 A DE2300853 A DE 2300853A DE 2300853 A1 DE2300853 A1 DE 2300853A1
Authority
DE
Germany
Prior art keywords
processing unit
address
order
line
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
DE19732300853
Other languages
German (de)
English (en)
Inventor
Frederik Zandveld
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Philips Gloeilampenfabrieken NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Gloeilampenfabrieken NV filed Critical Philips Gloeilampenfabrieken NV
Publication of DE2300853A1 publication Critical patent/DE2300853A1/de
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
    • G06F9/355—Indexed addressing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/02—Digital computers in general; Data processing equipment in general manually operated with input through keyboard and computation using a built-in program, e.g. pocket calculators
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3867—Concurrent instruction execution, e.g. pipeline or look ahead using instruction pipelines
    • G06F9/3869—Implementation aspects, e.g. pipeline latches; pipeline synchronisation and clocking

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Quality & Reliability (AREA)
  • Computing Systems (AREA)
  • Computer Hardware Design (AREA)
  • Hardware Redundancy (AREA)
  • Multi Processors (AREA)
  • Executing Machine-Instructions (AREA)
DE19732300853 1972-01-11 1973-01-09 Rechenmaschine, die in zwei teile aufgeteilt ist Pending DE2300853A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
NL7200354A NL7200354A (enrdf_load_stackoverflow) 1972-01-11 1972-01-11

Publications (1)

Publication Number Publication Date
DE2300853A1 true DE2300853A1 (de) 1973-07-19

Family

ID=19815130

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19732300853 Pending DE2300853A1 (de) 1972-01-11 1973-01-09 Rechenmaschine, die in zwei teile aufgeteilt ist

Country Status (9)

Country Link
JP (1) JPS5326784B2 (enrdf_load_stackoverflow)
BE (1) BE793802A (enrdf_load_stackoverflow)
CA (1) CA967287A (enrdf_load_stackoverflow)
DE (1) DE2300853A1 (enrdf_load_stackoverflow)
FR (1) FR2167871A5 (enrdf_load_stackoverflow)
GB (1) GB1376268A (enrdf_load_stackoverflow)
IT (1) IT974428B (enrdf_load_stackoverflow)
NL (1) NL7200354A (enrdf_load_stackoverflow)
SE (1) SE383571B (enrdf_load_stackoverflow)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5323819A (en) * 1976-08-18 1978-03-04 Hiro Miyake Jigs to form side gate type hot runner requiring no additional energy from outside
GB2036392A (en) * 1978-04-21 1980-06-25 Ncr Co Computer system having enhancement circuitry for memory accessing

Also Published As

Publication number Publication date
BE793802A (fr) 1973-07-09
FR2167871A5 (enrdf_load_stackoverflow) 1973-08-24
GB1376268A (en) 1974-12-04
JPS5326784B2 (enrdf_load_stackoverflow) 1978-08-04
JPS4881447A (enrdf_load_stackoverflow) 1973-10-31
IT974428B (it) 1974-06-20
NL7200354A (enrdf_load_stackoverflow) 1973-07-13
CA967287A (en) 1975-05-06
SE383571B (sv) 1976-03-15

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Legal Events

Date Code Title Description
OHW Rejection