WO1979000959A1

WO1979000959A1 - A computer system having enhancement circuitry for memory accessing

Info

Publication number: WO1979000959A1
Application number: PCT/US1979/000228
Authority: WO
Inventors: J Roberts; P Jeffs; N Patel
Original assignee: Ncr Co
Priority date: 1978-04-21
Filing date: 1979-04-12
Publication date: 1979-11-15
Also published as: DE2951405A1; JPS55500197A; GB2036392A; FR2423823A1

Abstract

A computer system having enhancement circuitry for memory accessing, and has particular application to a system in which the number of bits which can be processed at one time by the processor is less than the number of bits in either a data word stored in the memory or the address associated with it. In a computer system (10) in accordance with the invention, enhancement circuitry (42) is connected between two buses (18, 20) which respectively connect a microprocessor (12) to a main memory (14) and to peripheral subsystems (16). The microprocessor is arranged to fetch a data word in said memory by loading an address in address registers (50, 54, 58, 62, 66) included in said enhancement circuitry (42) and is arranged to store a data word in said memory by loading an address in said address registers and a data word in data registers (52, 56, 60, 64, 68) also included in said enhancement circuitry.

Description

OMPUTER SYSTEM HAVING ENHANCEMENT CIRCUITRY FOR MEMORY ACCESSING

Technical Field

This invention relates to a computer system of the kind including a plurality of memory locations each storing a data word and having an address associated with it, and a processor, which may be a microprocessor, for processing a predetermined maximum number of bits at one time.

Background Art

In a typical computer system of the kind specified, the processor or microprocessor frequently accesses the computer main memory by fetching instructions, by fetching data to be operated in accordance with such instructions, and by returning data to memory after being operated on. A great deal of processor time is generally required to effect a complete access or transfer of instructions and data between the main memory and the processor, particularly in cases where the memory stores data words each having a greater number of bits than the number of bits which can be operated on at one time by the processor, or where the addresses associated with the memory locations each have a greater number of bits than the number of bits which can be operated on at one time by the processor.

For example, if a microprocessor is capable of only receiving and operating on data operands 16 bits (e. g. 2 bytes) long, and if the main memory in the computer system has each data word address specified by 24 bits (3 bytes) and has data words each with a length of 32 bits (4 bytes), the microprocessor cannot fetch or operate on a whole data word in one processor cycle.

The above operations of a typical microprocessor of fetching and storing data in memory, as well as the many other operations performed by the microprocessor are controlled by microinstructions held in a control store of the microprocessor. To fully execute simple fetch or store microinstructions often requires that the microprocessor use several processor cycles to address, fetch and store data. The use of many processor cycles to accomplish simple yet frequent processor operations reduces the speed and capability of the microprocessor. Where one operand is to be operated on with another, and the operands begin at different bit locations within the fetched data words, the microprocessor must also properly align the data. Where operands are longer than a single data word in memory, the microprocessor must keep track of the number of bits fetched and compare that with the number of bits in the operand so that the microprocessor will be able to determine when it has accessed enough data bits from memory. These problems may be particularly acute when decimal arithmetic operations are to be performed by the microprocessor and many microinstructions and numerous fetches and stores are required to complete each operation.

Disclosure of the Invention

It is an object of the present invention to provide a computer system in which the problems discussed above are alleviated.

According to the invention there is provided a computer system of the kind including a memory having a plurality of memory locations, each memory location being arranged to store a data word and having an address associated with it, and a processor for processing a predetermined maximum number of bits at one time, said predetermined maximum number being less than the number of bits in at least one or other of a data word and the address associated therewith, characterized by enhancement circuitry external to said processor and responsive to said processor, said enhancement circuitry including address register means for storing the address of a memory location, and data register means for storing a data word to be fetched from or stored in said memory, said processor being arranged to fetch a data word in said memory by loading an address in said address register means and being arranged to store a data word in said memory means by loading an address in said address register means and a data word in said data register means. It should be understood that in a computer system in accordance with the immediately preceding paragraph the use of the enhancement circuitry eliminates much of the processor time which might otherwise be required for fetching and storing operations. While the enhancement circuitry accomplishes the fetching or storing of data words in memory, the processor is free to proceed with other operations. Thus, the enhancement circuitry increases the speed of the processor by performing certain processor operations itself and by permitting the processor to perform other operations while the memory is being accessed, and also permits the processor to be efficiently used with a memory having addresses and data words of significantly greater length than that which the processor is capable of receiving at one time.

According to one aspect of the present invention, the enhancement circuitry of a computer system in accordance with the last but one of the preceding paragraphs includes arithmeticlogic means. Such means can perform certain processor operations off-line to the processor. As a result, the number of processor operations performable by the computer system is increased, and data within memory can be fetched and operated on by the enhancement circuitry while the processor may proceed with other operations. Brief Description of the Drawings

One embodiment of the Invention will now be described by way of example with reference to the accompanying drawings, in which:- Fig. 1 is a simplified block diagram of a computer system including enhancement circuitry in accordance with the present invention;

Figs. 2A and 2B together form a detailed block diagram of part of the system of Fig. 1 showing in particular the enhancement circuitry;

Fig. 3 is a diagram depicting the contents of an address register within the enhancement circuitry illustrated in Figs. 2A and 2B.

Best Mode for Carrying out the Invention Referring to Fig. 1, the computer system 10 shown therein includes a microprocessor 12, a main memory 14, peripheral subsystems 16, a system internal transfer bus 18 for connecting the microprocessor 12 to main memory 14, and a microprocessor external interface bus 20 which connects the microprocessor 12 to the peripheral subsystems 16.

As is conventional, the microprocessor 12 includes an arithmetic logic unit (ALU) 26, a set of internal registers 28, a control unit 30 and a control store or memory 32, The main memory 14 can be a conventional semiconductor or core memory that stores data and programs which are to be used by the microprocessor 12. The peripheral subsystems 16 include devices such as card readers, flexible disc units, computer operator consoles and panels, printers and the like, all of which are generally controlled by the microprocessor 12. The lines illustrated as interconnecting the various components of the computer system 10 are data lines only. As should be apparent to those skilled fa the art, numerous control lines (not shown) also interconnect the illustrated components, with the signals carried by the control lines enabling and assuring synchronization of the components. In normal operation, a program stored in main memory

14 and comprising a set of higher level software instructions or macro instructions is accessed, one macroinstruction at a time, by the microprocessor 12. The microprocessor 12 receives each macroinstruction and in response thereto selects a microprogram or subroutine within control memory 32 of microprocessor 12 corresponding to that macroinstruction and comprising a set of microinstructions. The microinstructions are basic commands or machine-level Instnictlons. The computer operates in accordance with such machine-level Instructions to accomplish the program macroinstruction. The control unit 30 generates the necessary control signals to regulate the flow of data inside and outside of the microprocessor 12. The ALU 26 performs any necessary arithmetic or logic operations on data, and the internal registers 28 temporarily store data, such as before or after being operated on by the ALU 26.

The computer system as thus far described is conventional.

In accordance with the present invention, enhancement circuitry 42 is included in the computer system 10 and is connected to the microprocessor 12 and between the microprocessor external interface bus 20 and the internal transfer bus 18.

Referring now also to Figs. 2A and 2B, the enhancement circuitry 42 includes ten register circuits, namely an Address Register 50, an A Operand Data Register 52, a B Operand Address Register 54, a B Operand Data Register 56, a C

Operand Address Register 58, a C Operand Data Register 60, a Next Instruction Address Register 62, a Next Instruction Data Register 64, an Input/Output (I/O) Memory Address Register 66 and an Input/Output Memory Data Register 68.

Each of the registers 50, 52, 54, 56, 58, 60, 62, 64, 66 and 68 are connected between the buses 18 and 20. The registers are grouped in pairs, with one register In each pair

(registers 52, 56, 60, 64 and 68) storing data bits and the other register in each pair (registers 50, 54, 58, 62 and 66) storing address bits.

The A Operand Address Register 50 and the B Operand Address Register 54 are each capable of receiving a 24 bit address of a location in main memory 14 from which a data word is to be fetched. When the data word is fetched, it is stored in the 32 bit A Operand Data Register 52 or the 32 bit B Operand Data Register 56. The C Operand Address Register 58 Is a 24 bit register for receiving the address of a location in main memory 14 for storing a data word. The data word to be stored in main memory 14 is the 32 bit data word held in the C Operand Data Register 60. The Next Instruction Address Register 62 is a 24 bit register for holding an address specifying the memory location of the next software instruction which will be used by the microprocessor 12. When the Next Instruction Address Register 62 is loaded with an address by microprocessor 12, the instruction at that address is automatically fetched and stored in the Next Instruction Data Register 64.

The I/O Memory Address Register 66 also specifies a 24 bit address in main memory 14. Both the I/O Memory Addres Register 66 and the I/O Memory Data Register 68 are loaded by the microprocessor 12 in response to data received by the mlcroprocessor from a device within the peripheral subsystems 16, such as a card reader. When the I/O Memory Data Register 68 is loaded with a data word, that data word is in turn delivered to memory and stored at the location specified by the I/O Memory Address Register 66.

The data registers in the enhancement circuitry 42 are each capable of storing one complete data word fetched from or to be stored in a memory location in main memory 14 (each memory location storing a 32 bit data word). The enhancement circuitry has particular utility where the processor can receive less than one data word at a time, and in the disclosed embodiment the microprocessor 12 receives 16 bits at its input during each processor cycle.

As illustrated at the upper right-hand corner of each of the address registers 50, 54 and 58 by the loop and notation "±1", each of these address registers is capable of automatically incrementing or decrementing its stored numerical address by a binary "1 " each time a byte of data within its paired data register is transferred out during the operation of the enhancement circuitry 42. The particular reason for incrementing or decrementing the address will be described in greater detail later. However, to illustrate this incrementing or decrementing function and to also illustrate the contents of each of the address registers, reference can be had to Fig. 3.

In Fig. 3, the contents of the A Operand Address Register 50 are illustrated. Of the 24 address bits (labelled "0" to "23") held in register 50, the 22 bit locations on the left (the most significant bits) specify a single data word location in main memory 14. The 2 bit locations on the right (the least significant bits), designated the "byte pointer", indicate one of the bytes (8 bits) within the data word. Since each data word is 32 bits in length, the byte pointer will indicate one of four bytes. Each time the address register is incremented or decremented, a "1" is added or subtracted from the binary number represented by the two bits in the byte pointer. If the number in the byte pointer is initially at zero and is incremented four times, indicating all four bytes of the data word in the A Data Register have been transferred out by the microprocessor, a carry is generated to the third bit location, causing the address register 50 to cross a data word boundary and specify a new data word address, one memory address higher or lower than the first memory address. A new data word indicator signal is generated by the register 50 each time the third bit location changes, causing the enhancement circuitry 42 to automatically fetch the new data word.

If the microprocessor is initially fetching the second byte of the data word at the address loaded in the A Operand Address Register 50, the byte pointer will so indicate. The register 50 will then cross a word boundary after being incremented only three times.

The B Operand Address Register and C Operand Address Register are incremented or decremented in the same manner

Referring now again to Figs. 2A and 2B, the Next Instruction Address Register 62 is similar to the A, B and C Operand Address Registers except that, as illustrated by the loop and notation "+4", the Next Instruction Address Register 62 increments by four each time the Next Instruction Data Register 64 is emptied by the microprocessor.

The A, 3, and C Operand and Next Instruction Address Registers 50, 54, 58, and 62 may be implemented by conventional cascaded hexideclmal counter circuits, such as No. 10136 counter circuits sold by Motorola, Inc. of Phoenix, Arizona. The I/O Memory Address Register 66 and all the data registers do not automatically increment or decrement, and may be implemented by any suitable conventional register circuits.

The enhancement circuitry also includes, as Illustrated in Fig. 2B, a conventional ALU 70 which is external to the microprocessor 12 and which has two inputs, one input connected to receive the data within data register 52 one byte at a time and the other input connected to receive the data within register 56 one byte at a time. The ALU 70 can perform an arithmetic or logic operation, such as decimal arithmetic. For reasons which will become apparent later, registers 52 and 56 are each connected to the inputs of the external ALU 70 by 4-to-1 multiplexer (MUX) circuits 71 and 72. The multiplexer circuits 71 and 72 are controlled by the two bit byte pointers In the A Operand Address Register 50 and the B Operand Address Register

54, respectively. Fig. 3 illustrates the use of the two bits in the byte pointer of the A Operand Address Register 50 to provide the control inputs to the multiplexer 71. The output of the external ALU 70 is connected to the C Operand Data Register 60 so that the output from the external ALU 70 can be stored in the register 60.

To keep track of the number of bytes to be processed by the microprocessor 12 or the external ALU 70, a tally register circuit 73 (Fig. 2A) is employed. The tally circuit 73 is loaded by the microprocessor 12 and stores the total number of bytes which are to be processed during an execution of a given macroinstruction. As each byte of the data is processed, the number representing the bytes in the tally circuit 73 is decremented by one, as illustrated by the loop and notation "-1 " in Fig. 2A. The tally circuit 73 also includes a zero detection circuit for notifying the microprocessor 12 when the number of bytes in the tally circuit 73 has been decremented to zero, in a manner well understood in the art. The tally circuit 73, including the zero detection circuit, can be implemented by hexidecimal counter circuits, such as the commercially-available

No. 10136 counter circuits referred to previously.

An external control word register 74 receives a 16 bit control word from the microprocessor 12 and delivers the bits in the control word by means of control lines (not shown) to control inputs of the registers 50, 52, 54, 56, 58, 60, 62, 64, 66 and 68 and the external ALU 70. The control bits collectively specify the manner in which the enhancement circuitry 42 is to operate, and the control bits individually delivered to the register circuits and the ALU 70 condition or initialize those components for carrying out the specified enhancement circuitry operation. As will be more fully described later, the control word bits specify whether the address registers 50, 54 and 58 are to increment or decrement when bytes of data are transferred to or from the microprocessor 12 or ALU 70 by way of the registers, whether the ALU 70 is to be used, and if the ALU 70 is used, what arithmetic or logic operation is to be performed, as well as any other functions or operations which the enhancement circuitry 42 could be designed to perform.

The enhancement hardware also includes a control logic and timing circuit 80. The control circuit 80 is comprised of conventional components for providing the necessary clocking and synchronization signals to each of the individual circuits within the enhancement circuitry 42, and also controls the inputs and outputs to the register circuits and the external ALU 70, by appropriate gating to the buses 18 and 20. Thus, the control circuit 80 includes logic gates which decode control signals and basic clock signals from the microprocessor 12 in order to properly sequence the transfer of data to and from each of the registers in the enhancement circuitry 42, in a manner well understood in the art. Numerous control lines, not shown, connect the control circuit 80 to the microprocessor 12, to the buses 18 and 20, and to each of the individual circuits within the enhancement circuitry 42.

Turning now to the operation of the enhancement circuitry 42 as illustrated in Figs. 2A and 2B, the enhancement circuitry can assist or enhance the operation of the microprocessor 12 in any one of several ways. Although only three basic operations will be described in detail, it should be understood that the registers 50, 52, 54, 56, 58, 60, 62, 64, 66 and 68 and the external ALU 70 could be designed to accomplish many other operations within the scope of this invention. In any of the following operations, the external control word register 74 is first loaded by the microprocessor 12 to initialize the registers and the external ALU 70 to carry out the specified operation.

The first operation to be described is a fetch and store operation between the main memory 14 and the microprocessor 12. In this operation, data words from main memory 14 are fetched for the microprocessor 12, or data words from the microprocessor are stored in main memory. This operation can either be accomplished in a word mode or a byte mode.

In the word mode, an address is supplied by the microprocessor 12 to either one of the A and B Operand Address Registers 50 and 54. Since the address will be 24 bits long, several processor cycles will be taken to load the relevant address register. When the address register is completely loaded a resulting signal delivered to the control circuit 80 will cause the loaded address register to be gated to bus 18, and a message is carried by bus 18 to the main memory 14 for fetching the data word at the specified address. As a consequence, an entire data word is delivered to one of the data registers 52 and 56; the delivery of the entire data word is made during one memory access, and during this time the microprocessor 12 is not required to "wait" for the returning data, since the data is stored in one of the data registers rather than in an internal register within the microprocessor.

After a data word is fetched and stored in one of the data registers, the microprocessor 12 can in accordance with microinstructions within the control store 32 transfer the data word from the relevant data register to the microprocessor along bus 20, such as sixteen bits at a time, and after receiving all the data, can cause the enhancement circuitry 42 to fetch another data word by reloading the relevant address register.

If data words from the microprocessor 12 are to be stored in the main memory 14, the C Operand Address Register 58 is loaded with the address of a memory location, and when microprocessor loads the C Operand Data Register 60 with a data word, a resulting signal to the control circuit 80 gates the C Operand Address and Data Registers 58 and 60 to bus 18. The data word is delivered to and stored in memory 14 at the specified address. Repeated stores can be made by the microprocessor 12 by repeatedly reloading the C Operand Address and Data

Registers 58 and 60.

In the byte mode, a data field having a number of bits exceeding the 32 bit data word length can be fetched from or stored in main memory 14. The microprocessor 12 loads tally circuit 73 with the number of bytes in the data to be fetched from or stored in main memory. If, for example, data is to be fetched at an address specified in the A Operand Address Register 50, the enhancement circuitry 42 first fetches the entire data word at the specified address and stores the data word in the A Operand Data Register 52. The microprocessor 12 then transfers the data in the A Operand Data Register 52 to itself, with the byte number in tally circuit 73 decremented by one and the byte pointer incremented for each byte transferred. When a data word boundary is crossed and the data word address within A Operand Address Register 50 increases to the next higher address in main memory 14, a NEW DATA WORD INDICATOR signal from the address register 50 is delivered to the control circuit 80 and causes the address register to again be gated to the bus 18 and fetch the data word at the new address. The address register 50 will continue to increment its byte pointer and cause new data words to be fetched until the decrementing tally number reaches zero. At such time, the zero detection circuit within the tally circuit 73 indicates to the microprocessor 12 that the fetching of the data field is complete.

The B Operand Address and Data Registers 54 and 56 will fetch data words, and the C Operand Address and Data Registers 58 and 60 will store data words in the same fashion.

As determined by the control word in the external control word register 74, the byte pointer in the relevant address register may be decremented rather than incremented, in which case the data word at the next lov/er address in memory is accessed in memory when the byte pointer crosses a data word boundary.

From the above, it can be seen that the microprocessor 12, even though limited to receiving a fewer number of bits at one time than the number of bits in a data word, can access a full data word without repeatedly accessing main memory 14. Since a single direct access to memory 14 by the microprocessor

12 can take a relatively greater length of time (several processor cycles) than a transfer of data from or to the enhancement circuitry 42 by the microprocessor and since the microprocessor without the enhancement circuitry would have to access memory several times to fetch or store a single data word, a considerable saving in processor time is accomplished by the enhancement circuitry 42. When the data to be fetched or stored exceeds the length of the data word, the enhancement circuitry automatically fetches or stores data in the next higher or next lower memory address location, freeing the microprocessor 12 of the need to use processor time to send and receive repeated fetch or store messages. The next operation to be described is that in which data at one location in memory 14 can be moved to another memory location. The microprocessor 12 loads the number of bytes of data to be transferred in the tally circuit 73, loads in the A Operand Address Register 50 the memory location address from which the data is to be fetched, and then loads in the C Operand Address Register 58 the memory address location to which the data is to be moved. The enhancement circuitry 42 fetches the data word and stores it in the A Operand Data Register 52, and the microprocessor 12 transfers the data word to the C Operand

Data Register 60, with each byte transferred causing the byte pointers in the address registers 50 and 58 to Increment (or decrement). When the C Operand Data Register 60 is filled, the data word therein is stored fa main memory 14. Whenever the addresses in either the A or C Operand Address Registers 50 and 58 cross a data word boundary, a NEW DATA WORD INDICATOR signal is sent to control circuit 80, and the data word in the next higher (or lower) memory location is fetched or stored, respectively. The new data words are repeatedly fetched to the A Operand Data Register 52, transferred by the microprocessor

12 to the C Operand Data Register 56, and then stored back in main memory 14 until the byte number in the tally circuit 73 reaches a zero. During this entire period, the microprocessor is used only to transfer the data between registers, and no processor time is used for memory access.

In the third operation to be described, data is fetched from main memory 14 to the A and B Operand Data Registers 52 and 56 and is presented a byte at a time to the inputs of the external ALU 70. The ALU 70 operates on the data and stores the result of the operation at its output in the C Operand Data

Register 60. The A, B and C Address Registers 50, 54 and 58 and the tally circuit 73 are initially loaded by the microprocessor 12, The operation will otherwise proceed off-line to the microprocessor 12, with the address registers incrementing (or decrementing) their byte pointers by one each time a byte of data in the A and B Data Registers 52 and 56 is operated on and put into the C Operand Data Register 60. When a data word boundary is crossed, the new data word specified in the A or 3 Address Register 50 or 54 is automatically fetched from memory 14. When the C Operand Data Register 60 is filled, the data word is automatically stored in memory. During this operation, the microprocessor 12 Is completely free to proceed with other operations. It is only necessary that it initially load the external control register 74, the tally circuit 73, and the relevant address register and send appropriate sequencing signals to transfer the data to and from the registers and cause the ALU 70 to operate on the data.

The multiplexers 71 and 72 align the 4 bytes in each of the A and B Operand Data Registers 52 and 56 when they are inputted to the external ALU 70. For example, if in the operation to be performed by the external ALU 70, the first bytes of data to be operated on are the first byte in the A Operand Data Register 52 and the second byte in the B Operand Data Register 56, the multiplexer circuit 72 aligns the data in the B Operand Data Register 56 so that the second byte is received first by the ALU 70. The byte pointer in the relevant address registers will indicate initially the byte to be operated on first, and as mentioned earlier, the multiplexer circuits 71 and 72 are controlled by the 2 bit byte pointers in the A and B Address Registers 50 and 54. From the above, it can be seen that the external ALU 70 can be used to Increase the capability of the computer system 10 by providing operations that are not provided by the microprocessor ALU 26. The external ALU 70 can also be used to more efficiently provide operations that are already provided by the microprocessor ALU 26. If the operations are common and require frequent memory accessing, accomplishing both the accessing and the ALU operation within the enhancement circuitry 42 can result in significant savings in processor time. As mentioned earlier, the control word bits delivered by the external control word register 74 to the registers 50, 52, 54, 56, 58, 60, 62, 64, 66 and 68 and to the external ALU 70 are coded to designate which operations are to be performed. Also as mentioned earlier, many operations other than those discussed could be implemented by the enhancement circuitry

42 in accordance with the present invention, those described above being merely exemplary.

The Next Address and Data Instruction Registers 52 and 64, and the I/O Memory Address and Data Registers 66 and 68 also access the main memory 14, independently of the other registers. The Next Instruction Address Register 62 is loaded by the microprocessor 12 with the address in memory of the next software instruction or macroinstruction to be provided to the microprocessor. The instruction at that address is fetched into the Next Instruction Data Register 64. When the microprocessor 12 finishes with the current instruction, it transfers to itself the next instruction from register 64. The Next Instruction Address Register 62 then automatically increases by four, as mentioned earlier, to access the next higher data word address in main memory 14, and the instruction at that address is then placed in the Next Instruction Data Register 64.

Accordingly, if instructions are stored in memory 14 in sequential order, the fetching of the instructions is accomplished by the enhancement circuitry 42 and not the microprocessor 12. This results in a substantial time savings for each program instruction executed.

During normal computer operations, the microprocessor 12 from time to time will receive data, and addresses of memory locations for such data, from peripheral equipment connected to the bus 20, such as card readers. Such addresses and data are received by the microprocessor 12, which as mentioned earlier delivers the addresses and data to the I/O Memory Address and

Data Registers 66 and 68. When the loading of a data word in the I/O Memory Data Register 68 is completed, the I/O Memory Address and Data Registers 66 and 68 are gated to bus 18 by the control circuit 80 and that data word is then stored in main memory 14 at the address specified by the I/O Memory Address

Register 66. In this manner, the microprocessor 12 is relieved of the need to access memory 14 directly to store data received from peripheral equipment.

The I/O Address and Data Registers 66 and 68 are the only registers in the enhancement circuitry 42 used for this

I/O function. Otherwise, one or more of the paired A, B and C Operand Address and Data Registers would be needed for the I/O function, and if being used to fetch or store at the time of an I/O interrupt, it might be required that they be unloaded, their contents be saved, and then their contents be restored before resuming the interrupted fetch or store operation.

It should be understood that in the computer system 10 described above the speed and capability of the microprocessor 12 are increased by the use of the enhancement circuitry 42 or "hardware" external to the microprocessor 12 to accomplish selected, more frequently required operations which otherwise would be performed by the microprocessor executing microinstructions within its control store 32. The enhancement circuitry 42 can accomplish the selected operations with greater speed than the microinstructions within the control store 32, and the increased speed offsets any higher cost attributable to the addition of the enhancement circuitry.

Claims

Claims:

1. A computer system of the kind including a memory having a plurality of memory locations, each memory location being arranged to store a data word and having an address associated with it, and a processor for processing a predetermined maximum number of bits at one time, said predetermined maximum number being less than the number of bits in at least one or other of a data word and the address associated therewith, characterized by enhancement circuitry (42) external to said processor (12) and responsive to said processor, said enhancement circuitry (42) including address register means (50, 54,

58, 62, 66) for storing the address of a memory location, and data register means (52, 56, 60, 64, 68) for storing a data word to be fetched from or stored in said memory (14), said processor being arranged to fetch a data word in said memory by loading an address fa said address register means (50, 54, 58, 62, 66) and being arranged to store a data word in said memory means by loading an address in said address register means (50, 54, 58, 62, 66) and a data word in said data register means (52, 56, 60, 64, 68).

2. A computer system according to Claim 1, characterized in that said address register means (50, 54, 58, 62, 66) includes a first register (50) for storing address bits, and in that said data register means (52, 56, 60, 64, 68) includes a second register (52) for storing a plurality of data bytes, a portion of the bits in said first register (50) providing a byte pointer representing a number that designates one of the plurality of bytes stored in said second register (52).

3. A computer system according to Claim 2, characterized in that said first register (50) is arranged to change said byte pointer by one for each byte transferred from said second register (52).

4. A computer system according to Claim 3, characterized in that said first register (50) is so arranged that said byte pointer is represented by the least significant bits in said first register (50), with the remaining most significant bits specifying a memory location, the arrangement being such that the remaining most significant bits are changed by one when all of the bytes in said second register (52) are transferred by said processor (12) so that the remaining most significant bits specify a new memory location.

5. A computer system according to any one of Claims 2 to 4, characterized in that said enhancement circuitry (42) includes a tally circuit means (73) for storing the number of bytes to be transferred from said second register (52) by said processor, the number of bytes to be transferred being decremented by one each time a byte is transferred from said second register (52) by said processor.

6. A computer system according to Claim 5, characterized in that said tally circuit means (73) includes zero detection means for indicating to said processor when the number of bytes stored in said tally circuit means (73) has been changed to zero.

7. A computer system according to Claim 1, characterized in that said enhancement circuitry (42) includes arithmetic-logic means (70) for operating on data, having two data inputs and a data output, in that said data register means (52, 56, 60, 64, 68) comprises a first data register (52) for storing a first data word from memory and connected to one of said two data inputs, a second data register (56) for storing a second data word from memory and connected to the other of said two data inputs, and a third data register (60) for storing a third data word to be stored in memory and connected to said data output of said arithmetic-logic means (70), and in that said address register means (50, 54, 58, 62, 66) includes three address registers (50, 54, 58) which are respectively arranged to store the addresses associated with said first data register (52), said second data register (56), and said third data register (60).