DE2951405A1 - A computer system having enhancement circuitry for memory accessing - Google Patents

Description

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DlPL-ING. KURT KAHLER Augsburg, December 14th, 1979

Ulmer Straße 160 PATENT ADVERTISER _{Te | (0821} 405th 82} 55

FS via 053749

professional representative at the European Patent Office

My reference: Case 2588 / PCT-GER General Power of Attorney No. 26/69

International patent application PCT / ÜS79 / OO228 Applicant: NCR Corporation, Dayton, Ohio, USA Translation of the international patent application

A COMPUTER SYSTEM WITH AN ACCELERATION CIRCUIT FOR MEMORY ACCESS

Technical area

This invention relates to a computer system of the type having a plurality of storage locations which each store a data word and to which an address is assigned, as well as a processing unit, which may be a microprocessor for processing a predetermined maximum number of bits at a time.

Technical background

In a typical computer system of the type specified, the processing unit or the microprocessor intervenes often with fetching instructions, fetching data to be processed according to such instructions, and bringing back of the processed data to the main computer memory. Much of the processor time generally goes into this requires full access or full transfer of instructions and data between main memory and to effect the processing unit, in particular

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in cases where the memory stores data words each having a greater number of bits than that Number of bits that can be processed by the processor at a time, or where the memory locations are assigned addresses each has a greater number of bits than the number of bits that belong to a Time can be processed by the processor.

For example, can a microprocessor only receive and process data operands containing 16 bits (e.g. 2 bytes) and is a data word address in the main memory of the computer system with 24 bits (3 bytes) specified and the data words each have a length of 32 bits (4 bytes), then the microprocessor can in not extract or process an entire data word in a processing cycle.

The above operations of a typical microprocessor of fetching and storing data in a memory, like many other operations performed by the microprocessor, are performed by microinstructions controlled which in a control memory of the microprocessor are stored. Requires full execution of simple fetch or save microinstructions often that the microprocessor has several processor cycles used for addressing, retrieving and storing data. The use of many processor cycles performing simple but frequent processor operations reduces speed and performance of the microprocessor. If one operand is to be processed with another, the operands begin at different bit positions within the fetched data words, then the microprocessor must also have one make appropriate alignment of data. If operands are longer than a single data word in memory, then must

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the microprocessor continuously register the number of bits fetched and match them with the number of bits in Compare the operand so that the microprocessor is able to determine when it has enough data bits accessed from memory. These problems become particularly acute when performing decimal arithmetic operations to be performed by the microprocessor and many microinstructions and numerous fetch and store operations are required to fully perform each operation.

Disclosure of the invention

It is an object of the present invention to provide a computer system in which the above discussed problems are facilitated.

In accordance with the invention there is provided a computer system of the type which includes a memory having a plurality of of memory locations, each memory location being able to store a data word and being assigned an address and a processor (processing unit) for processing a predetermined maximum number of bits a point in time, said predetermined maximum number being less than the number of bits at least of a data word or the address assigned to it, characterized by an address outside of said processor arranged and responsive to said processor acceleration (or acceleration) circuit, which Speed-up circuit address register devices for storing the address of a memory location and data register means for storing any of the foregoing Has memory to be fetched or to be stored data word, the processor being designed in such a way that he finds a data word in said memory by loading an address into said address register means

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retrieves and also in such a way that it enables a data word to be stored in said memory devices by loading an address into said address register devices and a data word into said means Performs data register devices.

It can be seen that in a computer system according to the immediately preceding paragraph the use an acceleration switch eliminates much of the processor time that would otherwise be spent on fetch and save operations would be required. While the speed-up circuit is retrieving or storing data words in memory, the processor is free to continue with other operations. The acceleration circuit thus increases the speed of the processor in that it carries out certain processor operations itself and in that it enables the processor to perform other operations while the memory is being accessed will; it also allows the processor to be used efficiently with a memory that stores addresses and data words which have a much greater length than that which the processor at a point in time can receive.

According to one aspect of the present invention has the accelerator circuit of a computer system according to the penultimate of the previous paragraphs arithmetic ^ logical devices. Such devices can perform certain processor operations off-line to the processor. The result is that number of processor operations that can be carried out by the computer system is increased and that the data within the memory is fetched up by the speed-up circuit and can be processed while the processor can continue with other operations.

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Brief description of the drawings

One embodiment of the invention will now be for example, with reference to the accompanying drawings, in which:

Fig. 1 is a simplified block diagram of a computer system incorporating the speed-up circuit according to the present invention;

Figures 2A and 2B together form a detailed circuit diagram of part of the system of Figure 1; wherein in particular the accelerator circuit is shown;

Fig. 3 is a diagram illustrating the contents of an address register within that illustrated in Figs. 2A and 2B Accelerating circuit reproduces.

The best way to carry out the invention

Referring now to Figure 1, the computer system 10 is shown to be a microprocessor 12, a main memory 14, peripheral subsystems 16, an intra-system communication bus 18 for connecting the microprocessor 12 to main memory and a microprocessor-external interface bus 20 which connects the microprocessor 12 with the peripheral Subsystems 16 connects.

As usual, the microprocessor 12 has an arithmetic logic unit (ALU) 26, a group of internal ones Register 28, a control unit 30 and a control memory 32. The main memory 14 can be a conventional semiconductor or Be core memory which stores data and programs to be used by microprocessor 12.

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The peripheral subsystems 16 include devices such as Card readers, floppy disk units, computer operator controllers and fields, printers and the like, which are common can be controlled by the microprocessor 12.

The lines connecting the various units of the computer system are only data lines. Like that As should be apparent to those skilled in the art, numerous control lines (not shown) also connect the illustrated Units, the signals carried by the control lines activate the units and a synchronization of the units.

In normal operation, a group of software commands stored in the main memory 14 and a group a higher level program or program containing macroinstructions are accessed by the microprocessor 12, namely one Macro command at a time. The microprocessor 12 receives each macro command and dials in dependent thereon Microprogram or a subroutine within the control memory 32 of the microprocessor 12 from which microprogram corresponds to that macro instruction and consists of a group of micro instructions. The micro instructions are basic commands or machine language commands. The computer works according to such commands in machine language, to execute the program macro command. The control unit 30 generates the necessary control signals to control the flow of data inside and outside the Microprocessor to regulate. The ALU 26 carries out all the necessary arithmetic or logical operations the data by and the internal registers 28 temporarily store data before or after their processing by the ALU 26.

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The computer system described so far is known .

In accordance with the present invention, the speed-up circuit 42 is included in the computer system 10 and connected to the microprocessor 12 and between the Microprocessor-external interface manifold 20 and the internal transmission manifold 18 switched.

Reference is now also made to FIGS. 2A and 2B, which show that the speed-up circuit 4 2 also has ten register circuits, namely an address register 50, an A operand data register 52, a B operand address register 54, a B operand data register 56, a C operand address register 58, a C operand data register 60, a "next instruction" address register 62, a "next command" data register 64, an input * · / output (I / O) memory address register 66 and an input / output memory data register 68.

Each of the registers 50, 52, 54, 56, 58, 60, 62, 64, 66 and 68 are connected between the buses 18 and 20. The registers are grouped in pairs, with one register of each pair (registers 52, 56, 60, 64 and 68) Stores data bits and the other register of each pair (registers 50, 54, 58, 62 and 66) stores address bits.

The A operand address register. 50 and the B operand address register 54 can receive a 24-bit address of a memory location in the main memory 14, from which a data word is to be extracted. If the data word was fetched, then it is in the 23-bit A-operand data register 52 or the 32-bit B-operand data register 56.

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The C operand address register 58 is a 24-bit register for receiving the address of a memory location in the main memory 14 for storing a data word. The data word to be stored in the main memory 14 is a 32-bit data word which is in the C operand data register 60 is held.

The "next command" address register 62 is a 24-bit register that holds an address indicating the storage location of the next software command indicates which microprocessor 12 is to use. The "next command" address register 62 is loaded by the microprocessor 12 with an address, the one at that address Command is automatically fetched and stored in the "next command" data register 64.

The I / O memory address register 66 specifies also a 24-bit address in memory 14. Both the I / O memory address register 66 and the I / O memory data register 68 are dependent on by the microprocessor from a device within of the peripheral subsystems 16, for example, a card reader is loaded. When the I / O memory data register 68 is loaded with a data word, then the data word is delivered to the memory and to that through the I / O memory address register 66 is saved.

The data registers in the speed-up circuit 42 can store a complete data word, which was fetched from main memory 14 (each memory location storing a 32-bit data word) or which Word is to be stored in a memory location in main memory 14. The speed-up circuit 14 becomes special used when the processor can receive less than one data word at a time and at that disclosed In the embodiment, the microprocessor 12 receives 16 bits at its input during each processor cycle.

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As indicated by the loop and the +1 notation in the upper right corner of each address register 50, and 58, each of these address registers can automatically convert its stored numeric address increase or decrease a binary 1 each time a data byte belongs to the pair within the two Data register is transferred out during the operation of the speed-up circuit 42. The specific reason for increasing or decreasing the address will be described in more detail later. To illustrate this increase or decrease function and also for illustration however, reference may be made to FIG. 3 for the contents of each of the address registers.

In Fig. 3 is the contents of the A operand address register 50 illustrates. Of the 24 address bits (labeled 0 through 23) stored in register 50 are stored, give 22 bit positions from the left (the leading bits) a one-data word storage location in the Main memory 14. The 2 bit positions on the right (the least significant bits) are marked with "Byte pointer" denotes and indicates one of the bytes (8 bits) within the data word. Since each data word is 32 bits is long, the byte pointer indicates one of four bytes. Every time the address register increments or decrements a 1 is added or subtracted from the binary number represented by the two bits in the byte pointer.

The number in the byte pointer is initially 0 and becomes incrementing it four times, this indicates that all four bytes of the data word are in the A data register from the microprocessor have been transferred; a transfer to the third bit position is then generated, which causes the address register

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50 exceeds a data word limit and a new one Data word address specifies a memory address higher or lower than the first memory address. A new data word indication signal is received from the register 50 is generated every time the third bit position changes, which causes the speed-up circuit 42 automatically pulls out the new data word.

The microprocessor initially fetches the second byte of the data word in the A operand address register 50 stored address, the byte pointer also indicates this. The register exceeds 50 then the word limit after increasing it three times.

The B operand address register and the C operand address register are increased or decreased in the same way.

Referring again to Figures 2A and 2B, the "next command" address register is shown 62, which is similar to the A, B, and C operand address registers except that we loop through and the notation +4 indicated the "next command" address register 62 is incremented by four each time the "next instruction" data register 64 is entered by the microprocessor is emptied.

The A, B, and C operand and "next instruction" address registers 50, 54, 58 and 62 can each be designed as a conventional cascade hexadecimal counter circuit, for example as No. 10136 counter circuit as sold by Motorola Inc. of Phoenix, Arizona. The 1/0 memory address register 66 and increment all data registers

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or do not decrease automatically, they can be represented by any suitable known register circuit will.

As illustrated in FIG. 2B, the speed-up circuit also has a conventional ALU 70 which is external of the microprocessor and has two inputs, one of which is data input within the Data register 52 one byte at a time and the other input data within the register 56 and received one byte at a time. The ALU 70 can perform an arithmetic or logical operation such as a perform decimal calculation. For reasons that will become clear later, registers 52 and 56 are each marked with Inputs of the external ALU 70 via 4-to-1 multiplexer (MUX) Circuits 71 and 72 connected. The multiplexer circuits 71 and 72 are represented by the two-bit byte pointers in the Α operand address register 50 or the B operand address register 54 controlled. Figure 3 illustrates the use of the two bits in the byte pointer of the A operand address register 50 for generating control input signals for the multiplexer 71. The output of the external ALU 70 is connected to the C operand data register 60 so that the output from the external ALU 70 is in the register 60 can be saved.

To keep up to date with the number of microprocessor 12 or external ALU 70 to be processed Bytes, a label register circuit 73 (Fig. 2A) is provided. The labeling circuit 73 is is loaded by microprocessor 12 and stores the total number of bytes used during execution of a given Macro command is to be processed. As each byte of data is processed, the number becomes which the bytes are represented in the identification circuit 73 to 1

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decreased, as illustrated by the loop and the designation -1 in FIG. The identification circuit 73 also has a zero detection circuit for notifying the microprocessor 12 when the byte count in the flag register 73 has been decremented to zero in a manner known in the art is. The flag circuit 73 including the zero detection circuit can be represented by hexadecimal counter circuits such as commercially available No. 10136 counter circuits to the above Was referred to.

An external control word register 74 receives and provides a 16-bit control word from the microprocessor 12 the bits in the control word via control lines (not shown) to control inputs of registers 50, 52, 54, 56, 58, 60, 62, 64, 66 and 68 and the external ALU 70. The control bits collectively specify the way in which the Acceleration circuit 42 is to work and the individual data bits supplied to the register circuits and the ALU 70 represent the state of those components for performing a particular speed-up circuit operation on or trigger them. As will be described in detail later, the control word bits indicate whether the Address registers 50, 54 and 58 should be incremented or decremented when data bytes to or from microprocessor 12 or the ALU 70 should be transmitted by means of the registers, whether the ALU 70 is to be used, and if the ALU 70 is used, which arithmetic or logical operation is to be performed as well as all other functions or Operations that the accelerator circuit 42 may be constructed to perform.

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The acceleration hardware also includes control logic and timing circuitry 80. The control circuit 80 consists of the usual components for generating the necessary clock and synchronization signals for the individual circuits within the acceleration circuit 42 and also controls the inputs and outputs the register circuits and the external ALU 70 by suitable gate clocking of the bus lines 18 and 20. Thus, the control circuit has 80 logic elements, which control signals and basic clocksi ^ ftf ^ e from Microprocessor 12 decode the appropriate sequence of data transfers to and from each of the registers in the speed-up circuit 42 to control in a well-known manner. Connect numerous control lines not shown the control circuit 80 with the microprocessor 12, the buses 18 and 20 and each of the individual circuits within the speed-up circuit 42.

The mode of operation of the acceleration circuit 42 according to FIGS. 2A and 2B will now be discussed; the speed-up circuit can control the operation of the microprocessor 12 in one of several ways support or accelerate. Although only three basic operations are described in detail, it can be seen that that registers 50, 52, 54, 56, 58, 60, 62, 64, 66 and 68 and the external ALU 70 can be configured to perform many other operations as part of the Can perform the inventive idea. The external control word register is used first for each of the following operations 74 loaded by microprocessor 12 to the registers and external ALU 70 to that effect initially to suggest performing the special operation.

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The first operation to be described is a fetch and store function between main memory 14 and the microprocessor 12. In this operation, data words from the main memory 14 become for the microprocessor 12 fetched or data words stored by the microprocessor in the main memory. This operation can be performed in either a word mode or a byte mode.

In word mode, an address from microprocessor 12 is taken to either the A or B operand address register 50 or 54 supplied. Since the address is 24 bits long, it takes several processor cycles to convert load the appropriate address register. When the address register is fully loaded, a result signal is issued to the control circuit 80, which causes the loaded address register via an AND gate is connected to data bus 18 and a message is sent over bus 18 to main memory 14 to extract the data word from the specified address. As a result, it becomes a complete Data word in one of the data registers 52 and supplied; the delivery of the complete data word is performed during a memory access and during at this time it is not necessary for the microprocessor 12 to "wait" for the data to be returned, since the data is stored in one of the data registers and not brought into an internal register within the microprocessor will.

After a data word has been fetched and stored in one of the data registers, the microprocessor can in accordance with microinstructions within control store 32, the data word from the appropriate data register along The bus 20 is transmitted to the microprocessor as 16 bits at a time, and after all of the data

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have been received, the microprocessor 12 can cause the acceleration circuit 4 2 another data word for reloading the relevant address register pulls out.

If data words are to be stored by the microprocessor 12 in the main memory 14, then this will be C operand address register 58 with the address of a memory location loaded, and when the microprocessor loads the C operand data register 60 with a data word, connects a resulting signal to control circuit 80 the C operand address and data registers 58 and 60 via AND gates to the bus line 18. The data word is delivered in the memory 14 to the specified address and stored there. Repeated memories can be made by the microprocessor 12 by repeated reloading the C operand address and data registers 58 and 60 are performed.

In the byte operating mode, a data field whose number of bits exceeds the 32-bit data word length can be extracted from the Main memory 14 can be fetched out or stored in this. The microprocessor 12 loads the label register 73 with the number of bytes in the data to be fetched from the memory or to be stored in the main memory Data. For example, when data from an address specified in the A operand address register 50 are to be fetched, then the acceleration circuit 42 fetches the complete data word from the specified Address and store the data word in the A operand data register 52. The microprocessor then transmits the data in the A operand data register 52 with the number of bytes in the tag circuit 73 is decreased by 1 and the byte pointer is increased for each byte transferred. As soon as a data word limit is exceeded

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and the data word address within the A operand address register 50 increments to the next higher address in main memory 14, a "NEW DATA WORD DISPLAY" signal from the address register 50 is supplied to the control circuit 80 and causes the address register again via an AND gate with the Bus 18 is connected and the data word fetches out at the new address. The address register 50 sets the increment of its byte pointer and causes new data words to be fetched up to the decreasing identification number reaches the value zero. At this point the zero detection circuit shows within the Indicating circuit 73 to the microprocessor 12 that the fetching of the data field is finished.

The B operand address and data registers 54 and 56 fetch data and the C operand address and - Data registers 58 and 60 store data words in the same Wise. As determined by the control word in the external control word register 74, the byte pointer in the applicable address register are decreased and not increased, in which case the data word at the The next lower address in the memory is activated when the byte pointer exceeds a data word limit.

From the foregoing it can be seen that the microprocessor 12, although responding to the reception of fewer bits is limited at the same time as the number of bits in a data word, a whole data word without repeated access to the main memory 14 can get out. As a single direct access to the memory 14 through the microprocessor 14 may take a relatively large amount of time (several processor cycles) than a Data transfer from or to the accelerator circuit 42 by the microprocessor and there the microprocessor without the

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Acceleration circuit would have to drive the memory several times to fetch a single data word or it to store there, a considerable saving in processor time is achieved by the acceleration circuit 42. If the data to be fetched out or to be stored exceed the length of the data word, the acceleration circuit automatically fetches data from the next higher or next lower memory address space or stores this data there accordingly, whereby the microprocessor 12 is relieved of the need to spend processor time sending and receiving repeated fetch or To use memory messages.

The next operation to be described is that of transferring data from one location in memory 14 to another Storage location can be moved. The microprocessor loads the number of data bytes to be transferred into the Flag circuit 73, loads into the A operand address register 50 is the location address from which the data is to be fetched and loads into the C operand address register 58 is the memory address location to which the data is to be moved. The acceleration circuit 42 catches up Data word and stores it in the A operand data register 52, and the microprocessor 12 transfers the data word to the C operand data register 60, each Transferred bytes causes the byte pointers in the address registers 50 and 58 are increased (or decreased). If the C operand data register 60 is full, then the Data word therein is transferred to main memory 14. always if the addresses are in either the A or the C operand address register 50 or 58 exceed a data word limit, a "NEW DATA WORD DISPLAY" signal is sent to the control circuit 80 is sent and the data word in the next higher (or lower) memory location is fetched or stored there. The new data words are repeated

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fetched out to the A operand data register 52, dated Microprocessor 12 into C operand data register 56 and then stored back in the main memory 14 until the number of bytes in the flag circuit 73 reaches zero. During this entire period the Microprocessor 12 only used to transfer the data between registers and no processor time for memory access used.

In the third operation to be described, data is moved from main memory 14 into the A and B operand data registers 52 or 56 and fetched one byte at a time to the inputs of the external ALU 70 offered. The ALU 70 operates on the data and stores the result of the operation at its output in the C operand data storage register 60. The A, B and C address registers 50, 54 and 58 and the tag circuit 73 are initially loaded by the microprocessor 12. Otherwise the operation is carried out off-line by the microprocessor 12, the address registers increment (or decrement) their byte pointers by 1 each time a data byte is in the A and B data registers 52 and 56 has been processed and placed in the C operand data register 60. Will be a If the data word limit is exceeded, the new data word specified in the A or B address register 50 or 54 is used automatically fetched from the memory 14. If the C operand data register 60 is full, then the Data word automatically stored in the memory.

During this operation, the microprocessor 12 is completely free to perform other operations. It all that is necessary is to initially identify the external control register 74, the identifier circuit 73 and the appropriate address register loads and unloads suitable sequence control signals

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sends so that the data is transmitted to and from the registers and thus causes the ALU 70 works with the data.

Multiplexers 71 and 72 align the four bytes in each of A and B operand data registers 52 and 56, if they are entered in the external ALU 70. Are for example with the one to be executed by the external ALU 70 Operation the first data bytes to be processed, the first byte in the A operand data register 52 and the second byte in the B operand data register 56, then the multiplexer circuit 72 aligns the data in the B operand register 56 in such a way that the second byte is received by the ALU 70 first. The byte pointer in the applicable Address registers initially indicate the byte to be processed first and, as previously mentioned, the multiplexer circuits 71 and 72 are controlled by the 2-bit byte pointers in A and B address registers 50 and 54.

From the foregoing, it can be seen that the external ALU 70 can be used to increase the performance of the computer system 10 by offering operations which the microprocessor ALU 26 does not are provided. The external ALU 70 can also be used to make operations more efficient can already be offered by the ALU 26 microprocessor. Are these operations common and require frequent memory access? then accomplishes both the access and the ALU operation within the speed-up circuit significant savings in processing time.

As mentioned before, the external control word register 74 to registers 50, 52, 54, 56, 58, 60, 62, 64, 66 and 68 and the external ALU 70 supplied control

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word bits encoded to indicate which operations are to be performed. As previously stated, can many operations beyond those discussed by the speed-up circuit 42 in accordance with the present invention are introduced, the ones described above are merely exemplary.

The next address and data command registers 62 and 64 and the I / O memory address and data registers 66 and 68 access the main memory 14 independently of the other registers. The next instruction address register 62 is provided by the microprocessor 12 with the memory address for the next software command or macro command loaded, which is to be fed to the microprocessor. The command at this address is placed in the next command data register 64 brought out. When the microprocessor 12 completes the current command, it transmits the to itself next instruction from register 64. The next instruction address register 62 then automatically increases by 4, as mentioned above, to the next higher data word address in main memory 14 and the instruction at that address is then placed in the next instruction data register 64 brought.

Thus, commands in memory 14 are in sequence is stored, then the fetching of the instructions is carried out by the speed-up circuit 42 and not by the Microprocessor 12. This results in a considerable saving of time for each program instruction carried out.

During normal computer operations, the microprocessor 12 will from time to time receive data as well Addresses of storage locations for such data and that of peripheral units, such as card readers, which with the

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Manifold 20 are connected. Such addresses and dates are received by the microprocessor 12 which, as previously mentioned, sends the addresses and data to the I / O memory addresses and provides data registers 66 and 68. Is the loading of a data word into the I / O memory data register 68 then the I / O memory address and data registers are terminated 66 and 68 connected via AND gates to the bus line through the control circuit 80 and the data word is then stored in main memory at that of the I / O memory address register 66 is saved. In this way, the microprocessor 12 removes the need relieved of direct access to the memory 14 for storing data received from peripheral units.

The I / O address and data registers 66 and 68 are the only registers in the speed-up circuit 42 used for this I / O function. Otherwise it would be one or more of the paired A, B, and C operand address and data registers for the I / O function required and when this is used to fetch or save data at the time of an I / O interruption were used, they might be required to remain unloaded, that their contents be saved, and that its contents are restored before the interrupted retrieve or store operation is resumed.

It should be understood that in the computer system 10 described above, the speed and performance of the microprocessor 12 through the use of the speed-up circuit 42 or one external to the microprocessor 12 located hardware is increased in order to carry out selected more frequently required operations, which would otherwise be carried out by

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the microprocessor can be carried out with the execution of microinstructions within its control memory 32. The speed-up circuit 42 can perform the selected operations at a higher speed perform than the microinstructions within the control store 32 and the increased speed predominates any higher cost that can be attributed to adding the speed-up circuit.

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Claims (7)

Claims; Mj A computer system of the type which has a memory with a plurality of storage locations each of which is arranged in such a way that it stores a data word and is assigned an address is, as well as a processor for processing a predetermined maximum number of bits at a time, wherein the predetermined maximum number is lower than the number of bits in at least one data word or its assigned address, characterized by an acceleration circuit (42) which is external to the processor (12) and responsive to said processor, the speed-up circuit (42) address register means (50, 54, 58, 62, 66) for storing the address of a memory location and data register devices (52, 56, 60, 64, 68) for storing a to be fetched from said memory (14) or in it storing data word and wherein said processor is arranged such that it is loaded by loading a Address in said address register devices (50, 54, 58, 62, 66) can fetch a data word and such that by loading an address into said address register devices (50, 54, 58, 62, 66) and a word of data in said data register devices (52, 56, 60, 64, 68) a word of data in said Can store storage devices. 2. Computer system according to claim 1, characterized in that that said address register devices (50, 54, 58, 62, 66) have a first register (50) for Storing address bits and that said data register devices (52, 56, 60, 64, 68) have a second Register (52) for storing a plurality of bits of data 030606/001 8 295U05 has, some of the bits in said first register (50) providing a byte counter which is a Represents a number indicating one of a plurality of bytes stored in said second register (52) 3. Computer system according to claim 2, characterized in that said first register (50) is provided is to change said byte pointer by 1 for each transferred from said second register (52) Effect byte. 4. Computer system according to claim 3, characterized in that that said first register (50) is arranged in such a way that said byte pointer through the bits lowest value in said first register (50), where the remaining bits with higher significance specify a memory location and where the Arrangement is made so that the remaining bits with a higher significance are changed by 1 if all of the bytes in said second register (52) have been transferred by said processor (12) so that the remaining bits Specify a new memory location with higher priority. 5. Computer system according to one of claims 2 to 4, characterized in that said accelerating circuit (42) identifying circuit devices (73) for storing the number of times to be transmitted from said second register (42) by said processor Bytes, the number of bytes to be transmitted is decreased by 1 each time a byte of the said second register (52) has been transferred by said processor. 030606/0018 295U05 6. Computer system according to claim 5, characterized in that said identification circuit devices (73) Zero detection devices have to indicate to the named processor when the in the named Tag circuit means (73) has changed the number of bytes stored to zero. 7. Computer system according to claim 1, characterized in that that said acceleration circuit (42) arithmetic and logic devices (70) for processing of data, which has two data inputs and one data output, that said data register devices (52, 56, 60, 64, 68) a first data register (52) for storing a first data word from the memory which is connected to one of said two data inputs, and a second data register (56) for Storage of a second data word from the memory, which is connected to the other of the two data inputs mentioned is connected and a third data register (60) for storing a third data word which is in the memory is to be stored and which register with the named data output of the named arithmetic-logic device (70) and that said address register devices (50, 54, 58, 62, 66) have three address registers (50, 54, 58), which are arranged correspondingly to the said first data register (52), store addresses associated with said second data register (56) and said third data register (60). 030606/001 8