DE2704560C2 - Data processing system with parallel provision and execution of machine commands - Google Patents

Description

The invention relates to a data processing Ie System with several specialized, through microirograms controlled processors and with a common memory system in which the processing on machine commands that are also virtually addressed are usually carried out in parallel by a preparation processor carries out command reading and address calculation for command operands, and one connected Executive processor takes over the actual execution of commands ("Electronic Computing Systems", 1973, p. 60-65),

For the central units of commercial data processing systems are dependent on the performance class different structures for the processing units

In addition to processors with purely sequential command processing, i. H. a strict one Sequence of the functions »Execution of a / Ken machine command«, »Read the next (Vj-fl) -th machine instruction «,» Execution of the

ι> (n + 1) -th machine command, etc., processors with overlapping command processing are also known. Here, the fact is utilized that allows a processing cycle for a machine instruction at least in a retrieval and an execution phase divide In such processors is then the read operation for an (n +:) - \ m machine instruction executed in parallel for executing a nth machine instruction wherein /> 1 can be. This group of data processing systems also includes a device for processing machine commands of different formats in a micro-programmed data processing system, which is proposed in German patent application P 25 57 787. This device is used

jo machine commands provided hidden, d. H. already during the execution of a preceding machine instruction in a processing unit from the RAM read and cached in command buffers, the width of which is the interface to the RAM corresponds. In addition to a current command counter, the complete address of the machine instruction to be executed in the processing unit, another one with it associated pre-load command counter is provided.

This contains the memory address of the next machine command to be read out from each memory system. A comparison direction is connected to each of the two command counters, which also has an address register of the storage system is connected. This allows the validity of the content of the command buffer to be monitor discontinuous modifications of the current command counter. This avoids storage conflicts, in which the memory content of machine commands that have already been read out during the execution of a previous machine command is changed again.

Is even more pronounced, the parallel work in proces ^ eitungseinrichtungen the highest performance class, they are carried by many as so-called "pipeline" processors The structure derartigti ¹ processing units such. B. in the journal "Electronic Computing Systems", 1973, pages 60 to 65 in the article "Possibilities of accelerating a central unit through structural measures".

hQ Danagh the orders are like an assembly line edited what the term "pipeline" has come to be used for. For the individual processing phases, such as Reading a machine instruction, decoding, address calculation and provision of the instruction operand are

οι each one or more processing stations intended. The machine commands cycle through the chain of these processing stations and are then transferred to an executive processor. the

is structured analogously. The traffic with the storage system is the data processing The system is often handled by an autonomous storage access controller that controls the various Memory accesses during the entire processing cycle of a machine command or the parallel to must coordinate processing machine commands with each other.

Such a command assembly line requires a high level of circuit complexity for parallel work during the deployment and execution phases to achieve dat) with everyone as possible Machine cycle a machine command is finally executed. In each of these two phases are how described, generally several processing stations provided d. that is, there will be a relatively large number Machine commands with different processing statuses processed at the same time. The large number of these processors, which are powerful but very complex, is particularly disadvantageous possible memory or register conflicts. In addition, experience has shown that discontinuous modifications often occur a program sequence, z. B. in the event of program interruptions or fulfilled jump conditions, so that the machine instructions read into the assembly line in succession are then included in all of these Cases must be declared invalid.

For data processing systems of a medium performance class, this high effort is nn.! n justified, that of "pipeline" processors for controlling queues and conflict monitoring necessary is. The invention is therefore based on the object of a powerful data processing system of the type mentioned at the beginning, to which the following requirements are made:

The microprograms running in the executive processor or in the preparation processor must not be mutually exclusive hinder each other, therefore the accesses of both processors to the memory system or to the internal working registers of the executive processor can be easily coordinated. With discontinuous Program modifications must be read and preprocessed commands with certainty from excluded from execution, command processing must be as low as possible at the jump target Loss of time to be resumed. Memory and register conflicts themselves must be as simple as possible Recognized manner and, depending on this, read or read a modified machine command again. the address calculation and the provision of operands are repeated for him.

In the case of a data processing system of the type mentioned at the beginning, this object is achieved according to the invention solved by the features described in the characterizing part of the main claim.

The executive processor and the editing processor use a common register memory, which is implemented in the executive processor. This has the advantage that a modified executive processor The contents of the register do not also include a modification in an otherwise required corresponding register of the Editing processor means. Furthermore, the editing and executive processors can be a single one Use the interface to the storage system together without the need for an expensive priority control would be necessary. Also the monitoring of possible memory or register conflicts with the help of two Comparison facilities is relatively simple because held

relative to a sophisticated monitoring method criterion that is easy to realize is used, be machines that are not consecutively located in the storage system commands to suppress parallel processing.

A major factor in this is that no memory operands are set by the preparation processor of a machine instruction read in advance, but nui whose effective memory addresses are provided. Even register operands are only then direct provided if this is already possible within a short deployment phase or otherwise! cannot be read within the execution phase of a machine without additional expenditure of time could.

Finally, the hicrarchically structured microprogram control for the is of particular advantage Executive and editing processors from the loadable microprogram memory. The microprogram me of the executive processor ßehi; i in a suitable place Stcucr commands for reading a memory word or the register memory by the processing process')! away. thereby a mutual hindc Execution of the executive and editing processors are excluded from the storage system or on the register storage be sen. In the format of the microinstructions de; There are only two additional executive processors further bit positions required so that this advantage h ·. ixits will reach'.hi with very little effort.

Nevertheless, the microprogram memory of the executive processor is not with the detailed control de < Editing processor loaded, which means a considerable broadening of the microinstruction forinates because there is also a small state control memory provided in the preparation processor. The preparation processor is thus autonomous in relation to it the executive processor and can independently and depending on the needs of the acceptance of the Control commands transferred to the executive processor decide. Developments of the invention are in Subclaims characterized and are in the following description of an embodiment the invention explained in more detail.

For the description of this exemplary embodiment, the drawing serves as an explanation, and shows

Fig. 1 in a block diagram schematically the structure of a data processing system in which a Processor system according to the invention can be used,

F i g. 2 and F i g. 3 together show the embodiment of the preparation processor according to the invention and to it connected functional units of the data processing system,

4 and 5 based on function diagrams the Process of the preparation phase of the machine commands to be provided.

For a better understanding of the subject matter of the invention, FIG. 1 shows a block diagram of a data processing system, of which a device for processing commands forms part. The Anaige is divided into three larger functional units, a storage system S-SYST, a processor system P-SYST and an input / output system E / O-SYST.

The memory system S-SYST contains a working memory, preferably designed as a semiconductor memory, with a plurality of memory modules SP-M, which are controlled independently of one another via a working memory controller AST. A modular PSP buffer memory is also attached to this

connected. This Speiehcrhicrarchie allowed in typical Belriebsfall more than 95% of all .Speicherzugriffe from the fast buffer memory PSP to use and thus the effective access and cycle time of the storage system S-SYST much ^r to decrease.

As a visualization system, the processor system r'SYST contains at least one executive processor EP and a processing processor IIP integrated therewith, to which a microprogram load memory MPL is assigned. This contains the entire lunklioncllcn microprograms and can be designed, for example, as a flexible magnetic disk.

Finally, the! -In-ZAusgabc-System IyASYST can be microprogram control and possibly also use the loadable microprogram memory W (M. In addition to an input-output structure I ⁷ JA-ST byte and block multiplex channels IiY- MlIX or Hi.-MiJX, the functions are to be considered as special n-tcn transfer processors, in which the fin / output processes run independently of the processing system controlled by channel programs. The input / output control t '/ A-ST coordinates these Data transmission processes according to priority criteria.>■■>

After this based on FIG. The overview described in the present context is essentially interested in the processing system and here in particular the integrated processing processor IIP, since microprogrammed processing processors, such as the executive processor EP, can be assumed to be known per se. The preparation processor IIP is shown in two separate FIGS. 2 and 3, only for reasons of space. Both figures contain, as far as necessary for understanding, in addition to details of the processing processor IIP also schematically indicated further functional units of the data processing system, which are clearly highlighted here from the drawing by a dash-dotted border in order to establish the connection. i <>

The editing processor IIP integrated in the executive processor EP is intended to execute parallel to the processing of a machine command in the following function, which shortens the command execution, for the following machine commands / (n + // ': -r>

Reading of commands l (n + i) mh / = 2 ... 8 from the memory system S-SYST in a command buffer;
Provision of register operands for the command / Zn + I);

Calculation of effective memory addresses for the ^w or the memory operand of the instruction

Providing the first microinstruction for the command l (n + \).

In general, this can reduce the time it takes for the command to provide read access to Register operands and for address calculation can be saved.

According to FIG. 2, the preparation processor IIP contains a current command counter P made up of counter flip-flops, in which the effective address of a machine command to be executed is stored Comprises a length of two, four or six bytes, this instruction counter P is in a conventional manner by ± 2. Modify ± 4 or ± 6. An analog pre-load command counter PPI is also connected to it, which is also J byte wide and structured in an analog manner. This contains an effective memory address for reading commands. Its counter reading therefore usually has a lead in relation to the reading of the current command counter / ', which in this exemplary embodiment can be a maximum of 20 bytes. This command counter can be modified by + 2, +4 and +8. Its lead compared to the status of the current command counter P is displayed in a lead counter VLZ, which is designed as an up / down counter with a width of 4 bits. Its content is decreased by 1, 2 or 3, depending on the length of the machine command to be executed. Conversely, the counter country of the forward counter is increased by 1.2 or 4 when a new command word is read from the S-SYST memory system.

Two memory address comparators SVi and SV2 are also assigned to both command counters / 'and PPF. For all Sehreiboperalioncn in the S-SYST memory system, these compare the address for a machine command in the respectively connected command counter P or PPF with a memory address contained in a 3-byte-wide memory address register MA . This register is just like a memory data register MD with a length of 8 bytes in the executive processor fPangcordnel.

In Fig. 2 it is indicated schematically that the memory address register MA can be loaded from the preload instruction counter PPF, but also internally from the executive processor EP via memory address lines SAL. Its output is connected to the S-SYST storage system. During a read operation, the memory content defined by this register is read out and transferred to the memory data register MD, but also via a memory data line SDL 1 to the integrated processing processor IIP . For memory accesses by the executive processor EP , memory data to be written are transferred to the memory data register MD via wide memory data lines SDL 2 or read memory data are transferred to third memory data lines SDL 3 in the executive processor EP . If the executive processor EP now performs a write access to the S-SYST memory system, a memory conflict is possible each time. Such a memory conflict, in which a machine command that has already been read out in advance is written again, is detected by the two memory address comparators SV 1 and SV2 and indicated by a conflict signal MC . The forward counter VLZ is set to zero by the internal control of the integrated preparation processor IIP , even if the jump conditions are met, and so at the jump! the machine command is read with the address transferred to the memory address register MA. When the forward counter VLZ is set to zero , all machine commands transmitted in advance are considered invalid.

In Figure 3, as well as other structures of the integrated rendering processor IIP especially a 20 byte Synthesis instruction buffer IB with five, arranged in four stages registers of 4 bytes each width shown in the first step is to take two buffer registers IBD or IBE an instruction double word on the first Storage data line 5DL 1 directly from the S-SYST storage system. In the second stage, a further buffer register IBC takes over the content of one of the two buffer registers of the first stage and transfers them

a buffer register IBB of the third stage and to a further buffer register IBA in the fourth stage.

As already indicated, the machine instructions have a formal of two, four or six bytes and can therefore be aligned with a word or half-word boundary. The alignment of a machine command to be processed can be recognized from the status of bit positions 29 and 30 in the current command counter P, as will be explained later. This bit combination is evaluated in order to read out a machine command from the command buffer IB. So z. B. in a .in a word boundary WC aligned machine command with a format of 6 bytes, the complete content of the buffer register IBA of the fourth stage and the first two bytes 0 and I taken from the buffer register IBB of the third stage. If, however, such an instruction aligned on a halfword boundary HWG, the Puffprrptnstrr IRA rlpr viprtpn .Sliifp lpttiulirh flip hpiiipn bytes, all four latched bytes 0 removed 2 and 3 and the buffer register IBB of the third stage to the third

Three multiplexers are assigned to the command buffer IB for this read control. Command fields for the address calculation are output via a first multiplexer D-MUX for distance addresses with a width of 12 bits. The second multiplexer O-MUX is used to read out the operation code of a machine command and the register length encryption with 1 byte each. Such data are to be regarded as tax data in the strict sense of the word; Lines on which such data are transported are therefore shown with broken lines for identification. The control data read out via the second multiplexer O-MUX are, among other things, fed directly to the executive processor EP , which is only indicated schematically in FIG. 3, in order to initiate the microprogram required there for processing the machine command read out.

A third multiplexer R-MUX for registration addresses is 4 bits wide, is used to extract register address fields of the next machine command from the buffer registers IBA or IB of the fourth or third stage and is connected on the output side to the executive processor EP to control a register memory /? SP. All internal working registers of the executive processor / - ^ are summarized there.

In addition, a second comparison device, which is also connected to this register memory RSP , is connected to this third multiplexer R-MUX for register addresses. It consists of two register address comparators RVX and RV2, which compare the write addresses with the register addresses used to prepare a machine command for all write operations in the register memory. If a comparison is positive, this means that when an η-th machine command is executed, a register content is changed for a subsequent fn + 1) -th machine command, ie a register conflict occurs. A second conflict signal RC then emitted is used to initiate the repetition of the preparation for the (n + 1) -th machine command that has taken place in the preparation processor UP up to that point

An address computer unit AAD with a 24-bit binary adder is also provided in the integrated preparation processor IIP. This is fed on the one hand from the multiplexer D-MUX for distance addresses and on the other hand from a register RD for register addresses. The latter is in turn connected to the yarn register memory RSP of the executive processor EP and takes the basic and index values read from the register memory RSP.

^r > addresses or, in the case of pure register errors, also directly to the register operands. Via the first multiplexer D-MUX , the binary adder receives the offset addresses or the result of a first address calculation from the first of two to the

to the binary adder AAD connected to the address buffer registers ABA or ADB . During the address calculation itself, 12-bit wide offset addresses are padded to 24 bits with leading zeros, from the information coming from the register RD for register addresses.

r> mation, the more significant 8 bits are not included in the calculation. The result is a 24 Pit wide effective address that acting in one of the two as a queue address buffer Registcr ΛΒΑ h7u / A /? /? Is nipdprirplpfft

■ - - CJ c,

-Ί) The above has already referred to the various Format of machine commands pointed out, but not yet explained in more detail, that five groups machine instructions can be distinguished primarily with regard to the type of how and where the instruction operands are

r> are saved. In the following table 1 these five possible command types RR to 55 are expressed in relation to the respective storage medium for the operands:

hi table I.

Name of command type

code

RR Register Register Instructions 00

) i RX register storage instructions with 01

Indexing option

RS Register Save Instructions 10

5 / memory direct operand instructions 10

55 Memory Save Commands 11

The abbreviations mean

R: the register address of an operand.

Χ: the index register address of an operand.

/: an immediate operand contained in the instruction.

S: the memory address of an operand.

ΛΛ commands have a length of 2 bytes or - in other words - a half word. RX, RS and 57 commands are one word, i.e. 4 bytes. Finally, 55 commands consist of 3 half-words or 6 bytes. In

-, ο every machine command is this command format - in in table 1 as code - encoded in two bit positions of the operation field with 00, 01 and 11 respectively The necessary information for all necessary route switching can be obtained from this bit combination

be derived. For a machine command to be provided, it is in the current command counter Pan at the bit positions P29, P 30 mentioned.

For the provision of the data of a machine command in the address buffer registers ABA or / 455, the following can now be determined:

In the case of ÄÄ commands, the first operand R 1 from the first address buffer register ABA and the second operand R 2 from the second address buffer register ABB are transferred to the executive processor EP . With RX, PS and 5 / commands, the address for the memory operand is read from the second address buffer register ABB and with SS commands the address for the first memory operand is in the first address buffer.

Il

Register ABA and the one for the second memory operand in the second address buffer register ABB. It is stipulated that all eight more significant bit positions are set to zero if the two address buffer registers contain addresses.

In the introduction it was explained that the integrated editing processor IIP also uses the directly assigned loadable microprogram memory WCM of the executive processor EP , above all in order to avoid access conflicts. However, in order not to unnecessarily enlarge the format of the microinstructions of the loadable microprogram memory WCM , the entire control of the integrated editing processor /// 'is not taken over in detail. A status control memory ZSROM , which is designed as a read-only memory, is provided for the detailed control of the integrated processing processor. For this, only a relatively small micro-format of, for example, 2 bytes is required. so that a total of 1 Kbit is sufficient for the microprograms to be stored there.

The start address of a microprogram of the detailed control is formed as a function of the instruction format of the machine instruction and its relative position in a memory double word, ie its alignment in an address counter SRA assigned to this read-only memory. For this purpose, this address counter is connected to the command counter P via a 2-bit wide control line, from which it receives the two bit positions P 29, 30. The address counter SRA is connected via a further 2-bit wide control line to the output of the multiplexer O-MUX for the operation code, which supplies it with two bit positions IBQ, t as information about the operation code. The two least significant bit positions of the address counter SRA are filled with zeros. The address counter SRA is also directly connected to the loadable microprogram memory WCM of the executive processor EP via a 1-bit wide third control line. As indicated, a control command “read register memory” RRS can thus be transferred to the address counter SRA , with which the microprogram address is advanced in the state control memory ZS-ROM.

Microprogram controls are known per se, so the actual detailed control through the 16-bit microinstructions in the state control memory is not shown in FIG. 2 and 3 added. In Fig. 3, only one special feature is highlighted: Another read-only memory is the microprogram memory WP-ROM of a maintenance processor, which is otherwise not shown in detail. There maintenance functions are stored that are carried out by the operating system of the data processing system. During command execution - that is, in normal program execution - these are not required This is exploited and it is stored in this memory, the respective first microinstructions of proceeding in the executive processor EP microprograms for command execution This ensures that the first microinstruction of a machine instruction, such as the ( n + 1) -th machine command already provided during the execution of the previous n-th machine command and can be transferred to the executive processor at the end of the execution of this machine command. The microprograms for command processing in the executive processor EP can be controlled by the integrated

Preparation processor IIP, can be seamlessly joined together.

The device described with reference to FIGS. 2 and 3 allows the functions "reading a machine command", "address calculation, provision of a machine command" and "execution of a machine command" to be processed in an overlapping manner in three stages. The first two functions are overlapping in the integrated preparation processor IIPw \ d for successive machine commands, the third function, in the steady state, overlapping again in the executive processor £ V.

The sequence in the first two stages is illustrated below with reference to FIG. 4 and 5 explained in more detail. Both flow charts are related, the transitions of individual flow branches are therefore designated with identical letters A, B and C, respectively. Each block reproduces an elementary operation EO of a microprogram that runs either from your loadable microprogram memory WCM, the state control memory ZS-ROM or the microprogram memory WP-ROM of the maintenance processor. ¹ To make this clear, the individual elementary operations EO are, if necessary, additionally defined with these corresponding designations.

Discontinuous modifications of the current command counter P are caused, for example, by a program interruption or a fulfilled jump command. As already explained, the provision of the following machine command must then start again. As shown in FIG. 4, this process is controlled by the executive processor EP. If the jump condition / is met with the last elementary operation EO π when processing a machine command I η , then with the following elementary operation EO 1 a microprogram from the loadable microprogram memory WCMan runs. It comprises an address translation AF for the content of the current instruction counter P and the transfer of this register content to the preload instruction counter PPF.

In the elementary operation EO 2 , the function “Read command double word” RD1 runs from the S-SYSTab memory system, the content of the pre-load command counter PPF is increased by eight and the next effective memory address is set in this way.

In the third elementary operation EO3 , the read command double word IDWm is transferred to the command buffer / i? In addition, the loadable microprogram memory WCM issues a control command PF “read memory system” to the integrated processing processor HP , which then reads the next double-word command.

At this point in time, the machine command l (n + \) already read into the command buffer / Se is not yet made available in the address buffer registers ABA or ABB . Therefore, in the executive processor EP, ie on the execution level, in the subsequent elementary operation EO 4, a possibly repeated zero operation NOOP follows . At the same time, another control command RRS "Read register memory" is transferred to the integrated preparation processor IIP , so that an elementary operation then runs in parallel on the preparation level, which is controlled from the state control memory ZS-ROM. The first machine command I (n + 1) read is further processed step by step until it is made available for processing in the executive processor EP .

In detail, there can be three process branches A, B and C in the integrated processing processor IIP , which are shown in FIG. These sequences for the second functional level, ie on the provision level, depend on the command type RR, RX, RS, SI or SS and on the alignment of a command in the memory double word. In the case of a machine command aligned with a double word boundary DG »', the two bit positions 29 and 30 in the current command counter P have the bit combination ι 00 in this example. In the case of an alignment on a word boundary WG , the bit combination is called 10 and, in the case of an alignment on one of the two half- word boundaries HWG \ and HWG 2 in the double word, the bit combinations are 01 or 11. The type of bit combination determines one of the three process branches A, ß or C.

In the most important case, branch A, a machine command to be processed is aligned with a double word boundary DWG or the first half word boundary HWG 1; this is always the case in the steady state, while a different alignment is possible after discontinuous modifications. For each machine instruction type, the processes running during the three elementary operations EOAX, EOS1 and EO6X of this branch A are shown in the individual appropriately marked blocks in FIG. 5 specified.

Let us first consider /? Ä commands. With this type of B-i error, the two operands are in registers R 1 and R2 of the register memory RSP and are defined by register addresses. In the first elementary operation EO 41 of this branch of the process, the control command RRS "read register memory" issued by the loadable microprogram memory WCM is taken over by the integrated processing processor IIP and the contents of the second register R 2 are transferred from the register memory RSPm to the register RD for register operands. In the second elementary operation EOSi , this read register content is entered in the second address buffer register ABB . In addition, triggered by a further control command RRS, the other register operand is now also read from register R 1 and transferred to the first address buffer register ABA in the next elementary operation EO6X. Both register operands are now available, thereupon in the integrated preparation processor // Pein ready signal SRR is generated. This triggers the activation of the microprogram memory WP-ROM of the maintenance processor and reads out the first elementary operation EOY on the execution level for the provided machine command l (n + \) from it . The further execution of the command then runs, controlled from the loadable microprogram memory WCM, in the executive processor £ Vab. For the other command groups, the three elementary operations EOAX, EOSX and EO6X each have an analog, but type-specific format. In this context, however, a special feature should be noted: The other machine instructions can also contain operands that are stored in an operand register Ri or Rl or in an index register XX or X2 of the register memory RSP . Except for /? Commands, however, the editing processor IIP does not provide such an operand directly, but only its register address, and this operand is read by the executive processor EP during the processing phase. This has the essential advantage that the branch A considered here only ever needs the three elementary operations £ 041, 51 and 61, especially since it is easier to access the register memory RSP in one of the elementary operations of the execution phase in parallel with another step. In FIG. 5, therefore, only the more extensive address calculations for the other operands are shown for the sake of simplicity.

In the case of SS commands, for example, an effective memory address must be determined for both operands. For this purpose, in the three elementary operations, the contents of two base registers BX and B 2 are read out one after the other from the register memory RSP and are each transferred to the register RD for register operands. In the address arithmetic unit AAD , the associated offset address DX or D 2 of the operand is added to the respective base address. The results are one of the two address buffer registers ABA and OJ registered ir. At the end of the third elementary operator, this is fulfilled for both memory operands and a readiness signal SSS for this type of instruction is generated in the integrated preparation processor IIP. The provision of commands for RX, KS and SA commands should therefore be immediately recognizable from the flow chart. This also applies to the other two process branches B and C, in which the machine command is aligned with a word boundary WG or the second half- word boundary HWG 2 . A further detailed description of the elementary operations EO 42 to EO 72 or the elementary operations EO 43 to EO 83 therefore no longer appears necessary for a complete understanding.

Returning to the illustration in FIG . 4, it should be pointed out that the preamble with the elementary operations EOX to EO3 - how ready! indicated - only after discontinuous modifications in the current command counter P is required In the normal case, with constructive intermediate storage of successive machine commands in the command buffer IL

ι skipped this introductory phase or ready! during the processing phase of previous machine commands carried out.

In Fig. 4 this is indicated with a control signal / which is evaluated together with the readiness signal S. Occur both signal so closes the last ar EO EO η the processing phase of the machine instruction Add directly to the first EO EOL 'the processing phase of the next machine instruction I (n + 1). However, if the readiness signal S is missing after the last elementary operation £ Ond has elapsed , then zero operations NOOP are faded in until this signal occurs.

From the above explanations it became clear that the microprograms stored in the loadable microprogram memory WCM also trigger the processes in the integrated preparation processor IIP via certain signals, in particular the control commands RRS and PF. It remains

However, it is up to the integrated preparation processor III- whether it accepts the signals offered or not. In this way, on the one hand, the integrated preparation processor IIP and the executive processor EP can access shared memory

I coordinate directions, such as to the S-SVS7 "storage system or to the RSP register, and thus to simplify the controls in the interfaces.
On the other hand, the processes still run in the

15 16

The two processors IIP and EP are separately profitable compared to conventional ones, with one processing and independent processing, so they can be run in real parallel with central processing units equipped with processors. As the small scope of the detailed control without - as in the case of the "Pipeljnig" principle for the integrated preparation processor IIP and built-up machines - reveals its circuit structure after each processing, such a -> station is formed in buffer devices queue queues and actual parallel work is already carried out with little open - Need to become,
wall possible. It brings a significant performance

Here / ti. "» Lilait drawings

Claims (9)

Patent claims: I. Data processing system with several specialized processors controlled by microprograms and with a common memory system, in which the processing of also virtually addressed machine commands usually takes place in parallel, with a processing processor performing the command reading and the address calculation for command operands, and a connected executive processor takes over the actual command execution, characterized in that a loadable microprogram memory (WCM ) belonging to the executive processor (EP) also controls the process of providing the machine commands in the editing processor (IIP) in such a way that simultaneous accesses by the editing processor and the executive processor to its register memory (RSPf or For the storage system (S-SYST) it is avoided that the editing processor has its own small status control memory (ZM-ROM) which contains the microprograms for the detailed control of the editing processor Senior Citizen and the read operations are triggered by output from the loadable microprogram memory of the executive processor control signals that the rendering processor about a built-up of several successively arranged buffer registers (IBA to IBE) command m buffer (IB) zitn caching has addition of location ensures in advance from the storage system machine instructions , to which an address computer (AAD, ABB, ABA) is connected to provide ^ egisteroperands or effective addresses of memory operands and that two comparison devices (SVi, SV2 or RV \, RV2) are arranged, which compare memory or register addresses with the corresponding addresses in anticipation of machine instructions read in advance and if they match, a con Issue a conflict signal (MC or RC) , whereby machine commands read in advance in the preparation processor are invalid and then read again. 2. Data processing system according to claim I, characterized in that the preparation processor (IIP) for pre-reading machine commands from the memory system (S-SYST) also uses a memory address register (MA) arranged in the executive processor (EP) and in addition to a current command counter (P) with the effective address of a next for executing machine instruction (In) having an input connected to these Vorausiade command counter (PPF) which, when prefetching of machine instructions (l (n + m)) Sex to genüber the count of the current instruction counter a corresponding lead, the absolute size of which is recorded in a lead counter (VLZ) assigned to the pre-load command counter. 3. Data processing system according to claim 2, characterized in that the comparison direction provided in the preparation processor (IIP) (SV 1, SV2) contains two registers to avoid memory conflicts, which are connected to the current instruction counter (P) or to the preload instruction counter (PPF) and which contain the effective addresses of machine instructions stored there and which also parallel the memory address -Registers (MA) are connected, so that during a write operation of the executive processor (EP) it can be determined by an address comparison in the comparison device whether the write operation detects machine commands read in advance and, in this case, a conflict signal (MC) for write operations in the comparison device from the comparison device Memory system is issued with which the forward counter (VLZ) is set to zero and thus a renewed reading of the machine commands that have been declared invalid and temporarily stored in the command buffer (IB) is triggered. 4. Data processing system according to one of claims 1 to 3, characterized in that the command buffer (IB) has buffer registers arranged in four stages, of which in the first stage two registers (IBD or IBE) via a memory data line (SDL 1) directly are connected to the output of the memory system (S-SYST) and receive a read memory double word that the outputs of these two buffer registers are connected in parallel to the inputs of a third buffer register (IBC) of the second stage, the output side via a further buffer register (IBB) of the third stage is connected to the fifth buffer register (IBA) of the fourth stage. 5. Data processing system according to claim 4, characterized in that command fields which record the operation code of machine commands aligned on a half-word boundary (HWC) or a word boundary (WG) are assigned outputs of the fifth buffer register (IBA) to the inputs of a multiplexer \ O-MUX ) are connected for the operation code, the outputs of which are connected to the executive processor (EP) for the transfer of the operation code of a provided machine command, that the command fields for offset addresses of command operands are assigned to outputs of the fourth and fifth buffer registers (IBA or IBB), a multiplexer (D-MUX) for distance addresses is connected, the outputs of which are connected to the address arithmetic unit (AAD) , and that at the outputs of these two buffer registers, which are assigned to command fields for addresses of register operands, a multiplexer (R-MUX) for register Operand is connected, which is connected to the executive via address lines Processor contained register memory (RSP) is connected. 6. Data processing system according to claim 5, characterized in that to avoid register conflicts to the multiplexer (R-MUX) for register operands, the second comparison device (RVi, RV2) is connected, the two registers for the addresses of the register operands contains machine instruction to be processed and is also connected to the register memory (RSP) in the executive processor (EP) , so that during write operations of the executive processor in the register memory, the called address for an internal working register in the register memory with the addresses for register operands of the machine command to be provided is comparable and, if the comparison is positive, a conflict signal (RC) for write operations in the register memory is issued, which invalidates the previous preparation for the machine command concerned. 7. Data processing system according to claim 5 or 6, characterized in that the address arithmetic unit (AAD) connected to the multiplexer (D-MUX) for distance addressing is designed as a binary adder, which also has the outputs of a register (RD) parallel to the outputs of this multiplexer for register operands are supplied, which on the other hand is connected to the register memory (RSP) of the executive processor (EP) and that the outputs of the binary adder are provided with two address buffer registers (ABA, ABB) for register operands or effective addresses of operands Machine instruction are connected and the outputs of these registers are connected to the executive processor, the outputs of the first of the two registers (ABA) being fed back to the inputs of the binary adder via the multiplexer (D-MUX) for distance addresses. 8. Data processing system according to one of claims 5 to 7, characterized in that the state control memory (ZS- ROMX, which is designed as a read-only memory ) is assigned to the detailed control of the preparation processor (IIP) , as an address register, an address counter (SRA) is assigned to the Connected via a control line (IBO, 1) to the multiplexer (O-MUX) for the operation code for supplying a code about the type of machine command to be provided and via a further control line (7 * 29, 30) to the current command counter (P) is via which a bit combination characterizing the alignment of the machine command to be provided in a memory double word at a double word, word, first or second half word boundary (DWG, WG, HWG 1 or HWG 2) is transmitted and that the address counter is also transmitted to a third control line is connected, via which the state control memory from the loadable microprogram memory (WCM) of the executive processor (EP) a control command "read register memory" (RRS) can be supplied that triggers the reading of the next micro-command. 9. Data processing system according to claim 8, characterized in that a microprogram memory of another processor of the data processing system, the maintenance processor is connected to the state control memory (ZS-ROM), from which after the last elementary operation of a microprogram with which the Provision of a machine instruction is completed, the first microinstruction of the execution phase of the provided machine instruction is read out.